S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 332

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 8 S12X Debug (S12XDBGV3) Module
this triggers the state sequencer into the Final State, if configured for end alignment, setting the TRIG bit
disarms the module, ending the session. If breakpoints are enabled, a forced breakpoint request is issued
immediately (end alignment) or when tracing has completed (begin or mid alignment).
8.4.3.6
In case of simultaneous triggers, the priority is resolved according to
is suppressed. It is thus possible to miss a lower priority trigger if it occurs simultaneously with a trigger
of a higher priority. The trigger priorities described in
matches, the match on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that
a match leading to final state has priority over all other matches in each state sequencer state. When
configured for range modes a simultaneous match of comparators A and C generates an active match0
whilst match2 is suppressed.
If a write access to DBGC1 with the ARM bit position set occurs simultaneously to a hardware disarm
from an internal trigger event, then the ARM bit is cleared due to the hardware disarm.
8.4.4
The state sequencer allows a defined sequence of events to provide a trigger point for tracing of data in the
trace buffer. Once the S12XDBG module has been armed by setting the ARM bit in the DBGC1 register,
332
Highest
Priority
Lowest
State Sequence Control
Trigger Priorities
(Disarmed)
Match0 (force or tag hit)
Match1 (force or tag hit)
Match2 (force or tag hit)
Match3 (force or tag hit)
State 0
ARM = 0
External TAGHI/TAGLO
XGATE BKP
Source
ARM = 0
TRIG
Session Complete
MC9S12XE-Family Reference Manual Rev. 1.25
(Disarm)
ARM = 1
ARM = 0
Figure 8-22. State Sequencer Diagram
Table 8-42. Trigger Priorities
Trigger immediately to final state (begin or mid aligned tracing enabled)
Immediate forced breakpoint......(Tracing terminated immediately).
Trigger immediately to state 0 (end aligned or no tracing enabled)
Final State
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Trigger to next state as defined by state control registers
Table 8-42
State1
dictate that in the case of simultaneous
Table
Enter State0
State3
Action
8-42. The lower priority trigger
State2
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