S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 377

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Figure 10-25
Two concurrent threads are running on the system. One is running on the S12X_CPU and the other is
running on the RISC core. They both have a critical section of code that accesses the same system resource.
To guarantee that the system resource is only accessed by one thread at a time, the critical code sequence
must be embedded in a semaphore lock/release sequence as shown.
Freescale Semiconductor
set_xgsem: 1 is written to XGSEM[n] (and 1 is written to XGSEMM[n])
clr_xgsem: 0 is written to XGSEM[n] (and 1 is written to XGSEMM[n])
ssem:
csem:
gives an example of the typical usage of the XGATE hardware semaphores.
LOCKED BY
clr_xgsem
Executing SSEM instruction (on semaphore n)
Executing CSEM instruction (on semaphore n)
S12X_CPU
ssem &
set_xgsem
Figure 10-24. Semaphore State Transitions
MC9S12XE-Family Reference Manual Rev. 1.25
clr_xgsem
ssem & set_xgsem
UNLOCKED
csem
ssem
LOCKED BY
XGATE
csem
Chapter 10 XGATE (S12XGATEV3)
377