S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 466

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S912XET256J2VAGR

Manufacturer Part Number
S912XET256J2VAGR
Description
16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET256J2VAGR

Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
Chapter 10 XGATE (S12XGATEV3)
START_XGATE
DUMMY_ISR
XGATE_DATA_FLASH
XGATE_DATA_SCI
XGATE_DATA_IDX
XGATE_DATA_MSG
XGATE_CODE_FLASH
XGATE_CODE_DONE
XGATE_CODE_FLASH_END
XGATE_DUMMY_ISR_XG
10.9.3
To simplify the implementation of a program stack the XGATE can be configured to set RISC core register
R7 to the beginning of a stack region before executing a thread. Two separate stack regions can be defined:
One for threads of priority level 7 to 4 (refer to
466
Stack Support
MOVW 2,X+, 2,Y+
MOVW 2,X+, 2,Y+
MOVW 2,X+, 2,Y+
CPX
BLS
;###########################################
;#
;###########################################
MOVW #XGMCTL_ENABLE, XGMCTL
BRA
;###########################################
;#
;###########################################
RTI
CPU
;###########################################
;#
;###########################################
ALIGN 1
EQU
EQU
DW
EQU
DB
EQU
FCC
DB
;###########################################
;#
;###########################################
ALIGN 1
LDW
LDB
LDB
STB
LDB
STB
CMPL R4,#$0D
BEQ
RTS
LDL
STB
LDL
STB
RTS
EQU
MC9S12XE-Family Reference Manual Rev. 1.25
#XGATE_CODE_FLASH_END
COPY_XGATE_CODE_LOOP
*
XGATE
*
*-XGATE_DATA_FLASH
SCI_REGS
*-XGATE_DATA_FLASH
XGATE_DATA_MSG
*-XGATE_DATA_FLASH
"Hello World!
$0D
R2,(R1,#XGATE_DATA_SCI)
R3,(R1,#XGATE_DATA_IDX)
R4,(R1,R3+)
R3,(R1,#XGATE_DATA_IDX)
R0,(R2,#(SCISR1-SCI_REGS))
R4,(R2,#(SCIDRL-SCI_REGS))
XGATE_CODE_DONE
R4,#$00
R4,(R2,#(SCICR2-SCI_REGS))
R3,#XGATE_DATA_MSG;reset R3
R3,(R1,#XGATE_DATA_IDX)
(XGATE_CODE_FLASH_END-XGATE_CODE_FLASH)+XGATE_CODE_XG
DUMMY INTERRUPT SERVICE ROUTINE
START XGATE
XGATE CODE
XGATE DATA
Section 10.3.1.5, “XGATE Initial Stack Pointer for
;enable XGATE
;pointer to SCI register space
;string pointer
;ASCII string
;CR
;SCI -> R2
;msg -> R3
;curr. char -> R4
;R3 -> idx
;initiate SCI transmit
;initiate SCI transmit
;disable SCI interrupts
#
#
#
#
Freescale Semiconductor

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