S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 551

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

14.3.2.16 Pulse Accumulator A Flag Register (PAFLG)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
All bits reset to zero.
PAFLG indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (Reference TFFCA
bit in
14.3.2.17 Pulse Accumulators Count Registers (PACN3 and PACN2)
Freescale Semiconductor
Module Base + 0x0021
Module Base + 0x0022
PAOVF
Reset
Reset
Field
PAIF
1
0
Section 14.3.2.6, “Timer System Control Register 1
W
W
R
R
PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)
Pulse Accumulator A Overflow Flag — Set when the 16-bit pulse accumulator A overflows from 0xFFFF to
0x0000, or when 8-bit pulse accumulator 3 (PAC3) overflows from 0x00FF to 0x0000.
When PACMX = 1, PAOVF bit can also be set if 8-bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by
an active edge on IC3.
Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the IC7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at
the IC7 input pin triggers PAIF.
0
0
0
7
7
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference
System Control Register 1
= Unimplemented or Reserved
Figure 14-38. Pulse Accumulators Count Register 3 (PACN3)
Figure 14-37. Pulse Accumulator A Flag Register (PAFLG)
0
0
0
6
6
MC9S12XE-Family Reference Manual Rev. 1.25
Table 14-22. PAFLG Field Descriptions
0
0
0
5
5
(TSCR1)”.
NOTE
0
0
0
4
4
Description
(TSCR1)”).
0
0
0
3
3
Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
Section 14.3.2.6, “Timer
0
0
0
2
2
PACNT1(9)
PAOVF
0
0
1
1
PACNT0(8)
PAIF
0
0
0
0
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