S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 319

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

The trigger priorities described in
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
8.3.2.7.3
Read: If COMRV[1:0] = 10
Write: If COMRV[1:0] = 10 and S12XDBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 10. The state control register three selects the
targeted next state whilst in State3. The matches refer to the match channels of the comparator match
control logic as depicted in
by setting the comparator enable bit in the associated DBGXCTL control register.
Freescale Semiconductor
Address: 0x0027
SC[3:0]
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SC[3:0]
Reset
Field
3–0
W
R
These bits select the targeted next state whilst in State3, based upon the match event.
0
0
7
Debug State Control Register 3 (DBGSCR3)
Match1 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match2 triggers to State3....... Match0 triggers Final State....... Other matches have no effect
Match3 triggers to State3....... Match1 triggers Final State....... Other matches have no effect
Match0 triggers to State1....... Match1 triggers to State3....... Other matches have no effect
Match0 triggers to State1....... Match2 triggers to State3....... Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State3....... Other matches have no effect
Table 8-25. State2 —Sequencer Next State Selection (continued)
= Unimplemented or Reserved
Figure 8-11. Debug State Control Register 3 (DBGSCR3)
0
0
6
Match2 has no affect, all other matches (M0,M1,M3) trigger to Final State
Figure 8-1
Match3 triggers to Final State....... Other matches have no effect
MC9S12XE-Family Reference Manual Rev. 1.25
Table 8-26. DBGSCR3 Field Descriptions
Match3 triggers to State1....... Other matches have no effect
Match3 triggers to State3....... Other matches have no effect
Match2 triggers to State1..... Match3 trigger to Final State
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
Table 8-42
0
0
5
and described in
Any match triggers to Final State
dictate that in the case of simultaneous matches, the match
Any match triggers to state3
0
0
4
Description
Description
Section
SC3
0
3
8.3.2.8.1. Comparators must be enabled
Chapter 8 S12X Debug (S12XDBGV3) Module
SC2
0
2
SC1
0
1
SC0
0
0
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