S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 436

no-image

S912XET256J2VAGR

Manufacturer Part Number
S912XET256J2VAGR
Description
16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S912XET256J2VAGR

Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
Chapter 10 XGATE (S12XGATEV3)
LSR
Operation
n = RS or IMM4
Shifts the bits in register RD n positions to the right. The higher n bits of the register RD become filled
with zeros. The carry flag will be updated to the bit contained in RD[n-1] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
Code and CPU Cycles
436
N:
Z:
V:
C:
LSR RD, #IMM4
LSR RD, RS
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
Set if n > 0 and RD[n-1] = 1; if n = 0 unaffected.
Z
old
V
Source Form
^ RD[15]
C
new
0
0
n bits
MC9S12XE-Family Reference Manual Rev. 1.25
0
Address
Mode
IMM4
0
DYA
Logical Shift Right
0
0
0
0
0
0
0
0
RD
n
1
1
Machine Code
RD
RD
RS
IMM4
C
1
1
0
Freescale Semiconductor
1
1
LSR
0
0
1
1
Cycles
P
P

Related parts for S912XET256J2VAGR