S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 403

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

BFINSI
Operation
!RS1[w:0] ⇒ RD[w+o:o];
Extracts w+1 bits from register RS1 starting at position 0, inverts them and writes into register RD starting
at position o. The remaining bits in RD are not affected. If (o+w) > 15 the upper bits are ignored. Using
R0 as a RS1, this command can be used to set bits.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
BFINSI RD, RS1, RS2
N
∆
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
0; cleared.
Not affected.
Z
∆
w = (RS2[7:4])
o = (RS2[3:0])
V
0
Source Form
—
C
15
15
15
MC9S12XE-Family Reference Manual Rev. 1.25
Address
Mode
Bit Field Insert and Invert
TRI
7
0
1
W4
1
5
W4=3, O4=2
1
4
0
3
3
Machine Code
2
RD
O4
Inverted Bit Field Insert
0
0
0
RS1
RS2
RS1
RD
Chapter 10 XGATE (S12XGATEV3)
BFINSI
RS2
1
1
Cycles
P
403