S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 153

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

1. Read: Anytime.
1. Read: Anytime.
2.3.65
2.3.66
Freescale Semiconductor
Address 0x026C
Address 0x026D
Write: Anytime.
Write: Anytime.
PERJ
PPSJ
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
Port J pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset all pull device are enabled.
1 Pull device enabled.
0 Pull device disabled.
Port J pull device select—Determine pull device polarity on input pins
This register serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-
up or pull-down device if enabled.
1 A rising edge on the associated Port J pin sets the associated flag bit in the PIFJ register. A pull-down device is
0 A falling edge on the associated Port J pin sets the associated flag bit in the PIFJ register.A pull-up device is
PERJ7
PPSJ7
Port J Pull Device Enable Register (PERJ)
Port J Polarity Select Register (PPSJ)
connected to the associated Port J pin, if enabled by the associated bit in register PERJ and if the port is used as
input.
connected to the associated Port J pin, if enabled by the associated bit in register PERJ and if the port is used as
input.
1
0
7
7
PERJ6
PPSJ6
1
Figure 2-63. Port J Pull Device Enable Register (PERJ)
0
6
6
Figure 2-64. Port J Polarity Select Register (PPSJ)
Table 2-61. PERJ Register Field Descriptions
Table 2-62. PPSJ Register Field Descriptions
MC9S12XE-Family Reference Manual Rev. 1.25
PERJ5
PPSJ5
1
0
5
5
PERJ4
PPSJ4
1
0
4
4
Description
Description
PERJ3
PPSJ3
3
1
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PERJ2
PPSJ2
1
0
2
2
Access: User read/write
Access: User read/write
PERJ1
PPSJ1
1
0
1
1
PERJ0
PPSJ0
1
0
0
0
153
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(1)