S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 203

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

The reset value of 0xFD ensures that there is a linear RAM space available between addresses 0x1000 and
0x3FFF out of reset.
The fixed 4K page from 0x2000–0x2FFF of RAM is equivalent to page 254 (page number 0xFE).
The fixed 4K page from 0x3000–0x3FFF of RAM is equivalent to page 255 (page number 0xFF).
3.3.2.8
Read: Anytime
Write: Anytime
These eight index bits are used to page 1 KByte blocks into the EEPROM page window located in the local
(CPU or BDM) memory map from address 0x0800 to address 0x0BFF (see
accessing up to 256 KByte of EEPROM (in the Global map) within the 64 KByte Local map. The
EEPROM page index register is effectively used to construct paged EEPROM addresses in the Local map
format.
Freescale Semiconductor
Address: 0x0017
RP[7:0]
Reset
Field
7–0
W
R
EP7
RAM Page Index Bits 7–0 — These page index bits are used to select which of the 256 RAM array pages is to
be accessed in the RAM Page Window.
EEPROM Page Index Register (EPAGE)
1
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
EP6
1
6
Figure 3-15. EEPROM Page Index Register (EPAGE)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 3-14. RPAGE Field Descriptions
EP5
1
5
CAUTION
EP4
1
4
Description
EP3
1
3
Chapter 3 Memory Mapping Control (S12XMMCV4)
EP2
1
2
Figure
3-16). This supports
EP1
1
1
EP0
0
0
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