S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 336

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 8 S12X Debug (S12XDBGV3) Module
8.4.5.2.2
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it
however allows the filtering out of redundant information.
The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate
information from a looping construct such as delays using the DBNE instruction or polling loops using
BRSET/BRCLR instructions. Immediately after address information is placed in the Trace Buffer, the
S12XDBG module writes this value into a background register. This prevents consecutive duplicate
address entries in the Trace Buffer resulting from repeated branches.
Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in
most tight looping constructs. It does not inhibit repeated entries of destination addresses or vector
addresses, since repeated entries of these would most likely indicate a bug in the user’s code that the
S12XDBG module is designed to help find.
8.4.5.2.3
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. In the
case of XGATE tracing this means that initialization of the R1 register during a vector fetch is not traced.
This mode also features information byte entries to the trace buffer, for each address byte entry. The
information byte indicates the size of access (word or byte) and the type of access (read or write).
When tracing CPU12X activity in Detail Mode, all cycles are traced except those when the CPU12X is
either in a free or opcode fetch cycle. In this mode the XGATE program counter is also traced to provide
a snapshot of the XGATE activity. CXINF information byte bits indicate the type of XGATE activity
occurring at the time of the trace buffer entry. When tracing CPU12X activity alone in Detail Mode, the
address range can be limited to a range specified by the TRANGE bits in DBGTCR. This function uses
comparators C and D to define an address range inside which CPU12X activity should be traced (see
Table
When tracing XGATE activity in Detail Mode, all load and store cycles are traced. Additionally the
CPU12X program counter is stored at the time of the XGATE trace buffer entry to provide a snapshot of
CPU12X activity.
8.4.5.2.4
In Pure PC Mode, tracing from the CPU the PC addresses of all executed opcodes, including illegal
opcodes, are stored. In Pure PC Mode, tracing from the XGATE the PC addresses of all executed opcodes
are stored.
8.4.5.3
Referring to
information from the CPU12X. ADRH, ADRM, ADRL denote address high, middle and low byte
respectively. INF bytes contain control information (R/W, S/D etc.). The numerical suffix indicates which
tracing step. The information format for Loop1 Mode and PurePC Mode is the same as that of Normal
Mode. Whilst tracing from XGATE or CPU12X only, in Normal or Loop1 modes each array line contains
336
8-43). Thus the traced CPU12X activity can be restricted to particular register range accesses.
Table
Trace Buffer Organization
Loop1 Mode
Detail Mode
Pure PC Mode
8-43. An X prefix denotes information from the XGATE module, a C prefix denotes
MC9S12XE-Family Reference Manual Rev. 1.25
Freescale Semiconductor