S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 251

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

The resulting timing pattern of the external bus signals is outlined in the following tables for read, write
and interleaved read/write accesses. Three examples represent different access lengths of 1, 2, and n–1 bus
cycles. Non-shaded bold entries denote all values related to Access #0.
The following terminology is used:
5.4.2.4.1
Freescale Semiconductor
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
‘addr’ — value(ADDRx); small letters denote the logic values at the respective pins
‘x’ — Undefined output pin values
‘z’ — Tristate pins
‘?’ — Dependent on previous access (read or write); IVDx: ‘ivd’ or ‘x’; DATAx: ‘data’ or ‘z’
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
RW
Bus cycle ->
ECLK phase
ADDR[22:20] / ACC[2:0]
ADDR[19:16] / IQSTAT[3:0] ...
ADDR[15:0] / IVD[15:0]
DATA[15:0] (internal read)
DATA[15:0] (external read)
RW
Read Access Timing
...
...
...
...
...
addr 0
high
?
MC9S12XE-Family Reference Manual Rev. 1.25
Table 5-14. Read Access (n–1 Cycles)
...
...
...
...
...
...
...
Table 5-13. Read Access (2 Cycles)
...
...
...
...
...
...
...
1
Table 5-12. Read Access (1 Cycle)
iqstat-1
acc 0
low
addr 0
addr 0
?
z
high
high
?
?
1
?
?
1
1
1
addr 0
iqstat -1
high
iqstat-1
acc 0
acc 0
z
low
low
Access #0
?
1
Access #0
?
1
Access #0
z
z
z
z
2
iqstat 0
000
low
data 0
addr 0
addr 1
x
z
high
high
1
1
z
z
z
2
2
addr 0
iqstat 0
iqstat 0
high
acc 1
ivd 0
z
000
low
low
z
z
1
x
z
z
1
Chapter 5 External Bus Interface (S12XEBIV4)
3
0000
000
data 0
low
addr 2
data 1
addr 1
x
z
high
high
Access #1
Access #1
z
1
z
1
...
...
...
...
...
...
3
3
iqstat 1
acc 2
acc 1
0000
ivd 0
ivd 1
low
low
addr 1
z
z
1
z
z
1
high
Access #1
z
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
n
acc 1
ivd 0
0000
low
z
251
...
...
...
...
...
...