S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 362

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 10 XGATE (S12XGATEV3)
Module Base +0x0002
Read: Anytime
Write: In Debug Mode
10.3.1.3
The XGATE Channel Priority Level Register
In debug mode this register can be used to select a priority level when launching a thread (see
Section 10.6.1, “Debug
Module Base +0x0003
Read: Anytime
Write: In Debug Mode
10.3.1.4
The XGATE Initial Stack Pointer Select Register
to address “Module Base +0x0006”. A value of zero selects the Vector Base Register (XGVBR). Setting
1. Refer to
362
XGCHID[6:0]
XGCHPL[2:0]
Reset
Reset
Field
Field
6–0
2-0
W
W
R
R
Section 10.6.1, “Debug
Request Identifier — ID of the currently active channel
Priority Level— Priority level of the currently active channel
XGATE Channel Priority Level (XGCHPL)
XGATE Initial Stack Pointer Select Register (XGISPSEL)
0
0
0
0
7
7
Figure 10-5. XGATE Channel Priority Level Register (XGCHPL)
1
1
Features”).
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
6
6
Figure 10-4. XGATE Channel ID Register (XGCHID)
Features”
MC9S12XE-Family Reference Manual Rev. 1.25
Table 10-4. XGCHPL Field Descriptions
Table 10-3. XGCHID Field Descriptions
0
0
0
5
5
(Figure
(Figure
0
0
0
4
4
Description
10-5) shows the priority level of the current thread.
Description
XGCHID[6:0]
10-6) determines the register which is mapped
0
0
0
3
3
0
0
2
2
XGCHPL[2:0]
Freescale Semiconductor
0
0
1
1
0
0
0
0