S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 698

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 19 Pulse-Width Modulator (S12PWM8B8CV1)
19.3.2.2
The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the
PWMPOL register. If the polarity bit is one, the PWM channel output is high at the beginning of the cycle
and then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts
low and then goes high when the duty count is reached.
Read: Anytime
Write: Anytime
19.3.2.3
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described
below.
698
Module Base + 0x0001
PPOL[7:0]
PWME1
PWME0
Reset
Field
Field
7–0
1
0
W
R
PPOL7
Pulse Width Channel 1 Enable
0 Pulse width channel 1 is disabled.
1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when
Pulse Width Channel 0 Enable
0 Pulse width channel 0 is disabled.
1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when
Pulse Width Channel 7–0 Polarity Bits
0 PWM channel 7–0 outputs are low at the beginning of the period, then go high when the duty count is
1 PWM channel 7–0 outputs are high at the beginning of the period, then go low when the duty count is
PWM Polarity Register (PWMPOL)
PWM Clock Select Register (PWMCLK)
0
7
PPOLx register bits can be written anytime. If the polarity is changed while
a PWM signal is being generated, a truncated or stretched pulse can occur
during the transition
its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line0 is disabled.
reached.
reached.
its clock source begins its next cycle.
PPOL6
0
6
Table 19-2. PWME Field Descriptions (continued)
Figure 19-4. PWM Polarity Register (PWMPOL)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 19-3. PWMPOL Field Descriptions
PPOL5
0
5
PPOL4
NOTE
0
4
Description
Description
PPOL3
0
3
PPOL2
0
2
PPOL1
Freescale Semiconductor
0
1
PPOL0
0
0