S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 683

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

18.3.0.4
Read: Anytime
Write: Anytime
18.3.0.5
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0003
Module Base + 0x0004
PMUX[3:0]
PINTE[3:0]
Reset
Reset
Field
Field
3:0
3:0
W
W
R
R
PIT Multiplex Bits for Timer Channel 3:0 — These bits select if the corresponding 16-bit timer is connected to
micro time base 1 or 0. If PMUX is modified, the corresponding 16-bit timer is switched to the other micro time
base immediately.
0 The corresponding 16-bit timer counts with micro time base 0.
1 The corresponding 16-bit timer counts with micro time base 1.
PIT Time-out Interrupt Enable Bits for Timer Channel 3:0 — These bits enable an interrupt service request
whenever the time-out flag PTF of the corresponding PIT channel is set. When an interrupt is pending (PTF set)
enabling the interrupt will immediately cause an interrupt. To avoid this, the corresponding PTF flag has to be
cleared first.
0 Interrupt of the corresponding PIT channel is disabled.
1 Interrupt of the corresponding PIT channel is enabled.
PIT Multiplex Register (PITMUX)
PIT Interrupt Enable Register (PITINTE)
0
0
0
0
7
7
0
0
0
0
6
6
Figure 18-7. PIT Interrupt Enable Register (PITINTE)
Figure 18-6. PIT Multiplex Register (PITMUX)
MC9S12XE-Family Reference Manual Rev. 1.25
Table 18-5. PITMUX Field Descriptions
Table 18-6. PITINTE Field Descriptions
0
0
0
0
5
5
0
0
0
0
4
4
Description
Description
PINTE3
PMUX3
0
0
3
3
Chapter 18 Periodic Interrupt Timer (S12PIT24B4CV2)
PMUX2
PINTE2
0
0
2
2
PMUX1
PINTE1
0
0
1
1
PMUX0
PINTE0
0
0
0
0
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