S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 282

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 7 Background Debug Module (S12XBDMV2)
7.3
7.3.1
Table 7-2
7.3.2
A summary of the registers associated with the BDM is shown in
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
282
0x7FFF00
0x7FFF01
0x7FFF02
0x7FFF03
0x7FFF04
0x7FFF05
0x7FFF06
Address
Global
Memory Map and Register Definition
shows the BDM memory map when BDM is active.
Module Memory Map
Register Descriptions
BDMCCRL R
Reserved
Reserved
Reserved
Reserved
Reserved
BDMSTS
Register
Name
0x7FFF0C–0x7FFF0E
0x7FFF00–0x7FFF0B
0x7FFF10–0x7FFFFF
Global Address
0x7FFF0F
W
W
W
W
W
W
W
R
R
R
R
R
R
ENBDM
CCR7
Bit 7
X
X
X
X
X
X
MC9S12XE-Family Reference Manual Rev. 1.25
Figure 7-2. BDM Register Summary
= Unimplemented, Reserved
= Indeterminate
BDMACT
CCR6
Table 7-2. BDM Memory Map
X
X
X
X
X
6
Family ID (part of BDM firmware ROM)
CCR5
X
X
X
X
X
5
0
BDM firmware ROM
BDM firmware ROM
BDM registers
Module
CCR4
SDV
X
X
X
X
X
4
Figure
TRACE
CCR3
X
X
X
X
X
3
0
7-2. Registers are accessed by
= Implemented (do not alter)
= Always read zero
CLKSW
CCR2
X
X
X
X
X
2
Freescale Semiconductor
(Bytes)
Size
UNSEC
240
12
CCR1
3
1
X
X
X
X
1
0
CCR0
Bit 0
X
X
X
X
0
0