S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 530

• Manufacturer Part Number: S912XET256J2VAGR
• Description: 16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
• Manufacturer: Freescale Semiconductor

Specifications of S912XET256J2VAGR

• Core: HCS12X
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 256 KB
• Data Ram Size: 16 KB
• On-chip Adc: Yes
• Package / Case: LQFP
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Interface Type: CAN, SCI, SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 119
• Number Of Timers: 25
• Program Memory Type: Flash
• Supply Voltage - Max: 1.98 V, 2.9 V, 5.5 V
• Supply Voltage - Min: 1.72 V, 2.7 V, 3.13 V

Chapter 14 Enhanced Capture Timer (ECT16B8CV3)
14.2.3
This pin serves as input capture or output compare for channel 5.
14.2.4
This pin serves as input capture or output compare for channel 4.
14.2.5
This pin serves as input capture or output compare for channel 3.
14.2.6
This pin serves as input capture or output compare for channel 2.
14.2.7
This pin serves as input capture or output compare for channel 1.
14.2.8
This pin serves as input capture or output compare for channel 0.
14.3
This section provides a detailed description of all memory and registers.
14.3.1
The memory map for the ECT module is given below in the
is the address offset. The total address for each register is the sum of the base address for the ECT module
and the address offset for each register.
14.3.2
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Details of register bit and field function follow the register
diagrams, in bit order.
530
Memory Map and Register Definition
IOC5 — Input Capture and Output Compare Channel 5
IOC4 — Input Capture and Output Compare Channel 4
IOC3 — Input Capture and Output Compare Channel 3
IOC2 — Input Capture and Output Compare Channel 2
IOC1 — Input Capture and Output Compare Channel 1
IOC0 — Input Capture and Output Compare Channel 0
Module Memory Map
Register Descriptions
For the description of interrupts see
MC9S12XE-Family Reference Manual Rev. 1.25
NOTE
Section 14.4.3, “Interrupts”.
Table
14-2. The address listed for each register
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