S912XET256J2VAGR Freescale Semiconductor, S912XET256J2VAGR Datasheet - Page 249
S912XET256J2VAGR
Manufacturer Part Number
S912XET256J2VAGR
Description
16-bit Microcontrollers - MCU Watchdog OSC/Timer -40 C to + 105 C HCS12X MCU SPI
Manufacturer
Freescale Semiconductor
Datasheet
1.S912XEQ512J3CAGR.pdf
(1324 pages)
Specifications of S912XET256J2VAGR
Core
HCS12X
Data Bus Width
16 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
256 KB
Data Ram Size
16 KB
On-chip Adc
Yes
Package / Case
LQFP
Mounting Style
SMD/SMT
A/d Bit Size
12 bit
A/d Channels Available
24
Interface Type
CAN, SCI, SPI
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
- 40 C
Number Of Programmable I/os
119
Number Of Timers
25
Program Memory Type
Flash
Supply Voltage - Max
1.98 V, 2.9 V, 5.5 V
Supply Voltage - Min
1.72 V, 2.7 V, 3.13 V
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1. Incl. S12X_EBI registers
2. Refer to S12X_MMC section.
3. If EWAIT enabled for at least one CSx line (refer to S12X_MMC section), the minimum number of external bus cycles is 3.
4. Available only if configured appropriately by ROMON and EROMON (refer to S12X_MMC section).
5.4.2
Internal visibility allows the observation of the internal CPU address and data bus as well as the
determination of the access source and the CPU pipe (queue) status through the external bus interface.
Internal visibility is always enabled in emulation single chip mode and emulation expanded mode. Internal
CPU accesses are made visible on the external bus interface except CPU execution of BDM firmware
instructions.
Internal reads are made visible on ADDRx/IVDx (address and read data multiplexed, see
Table
show the type of access. External read data are also visible on IVDx.
During ‘no access’ cycles RW is held in read position while LSTRB is undetermined.
All accesses which make use of the external bus interface are considered external accesses.
Freescale Semiconductor
Data direction signals
threshold enabled on
Data select signals
(if 16-bit data bus)
address access
Reduced input
External wait
Chip Selects
(if Enabled)
Bus signals
Properties
Flash area
5-14), internal writes on ADDRx and DATAx (see
feature
Internal Visibility
(4)
Single-Chip
Normal
Single-Chip Modes
—
—
—
—
—
—
—
Table 5-9. Summary of Functions (continued)
MC9S12XE-Family Reference Manual Rev. 1.25
Single-Chip
Special
—
—
—
—
—
—
—
Signal Properties
ADDR[22:1]
DATA[15:0]
Expanded
Table 5-4
Normal
Refer to
EWAIT
UDS
LDS
CS0
CS1
CS2
CS3
WE
RE
—
Table 5-15
ADDR[22:20]/
ADDR[19:16]/
Single-Chip
ADDR[15:0]/
IQSTAT[3:0]
DATA[15:0]
DATA[15:0]
Emulation
IVD[15:0]
ACC[2:0]
ADDR0
LSTRB
1 cycle
EWAIT
RW
Chapter 5 External Bus Interface (S12XEBIV4)
—
—
Expanded Modes
to
Table
ADDR[22:20]/
ADDR[19:16]/
5-17). RW and LSTRB
ADDR[15:0]/
IQSTAT[3:0]
Emulation
Expanded
DATA[15:0]
DATA[15:0]
IVD[15:0]
ACC[2:0]
ADDR0
LSTRB
1 cycle
EWAIT
EWAIT
CS0
CS1
CS2
CS3
RW
Table 5-12
ADDR[22:0]
DATA[15:0]
Table 5-4
Special
Refer to
ADDR0
1 cycle
LSTRB
Test
RW
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