MC68332GCEH20 Freescale Semiconductor, MC68332GCEH20 Datasheet - Page 153

• Manufacturer Part Number: MC68332GCEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

6.5 QSM Initialization
MC68332
USER’S MANUAL
After reset, the QSM remains in an idle state until initialized. A general sequence guide
for initialization follows.
A. Global
B. Queued Serial Peripheral Interface
C. Serial Communication Interface (SCI)
1. Configuration register (QSMCR)
2. Interrupt vector and interrupt level registers (QIVR and QILR)
3. Port data and data direction registers (PORTQS and DDRQS)
4. Assign pin functions by writing to the pin assignment register (PQSPAR)
1. Write appropriate values to QSPI command RAM.
2. QSPI control register zero (SPCR0)
3. QSPI control register one (SPCR1)
4. QSPI control register two (SPCR2)
5. QSPI control register three (SPCR3)
6. To enable the QSPI, set the SPE bit in SPCR1.
1. SCI control register zero (SCCR0)
2. SCI control register one (SCCR1)
a. Write an interrupt arbitration priority value into the IARB field.
b. Clear the FREEZE and/or STOP bits for normal operation.
a. Write QSPI/SCI interrupt vector into QIVR.
b. Write QSPI (ILSPI) and SCI (ILSCI) interrupt priorities into QILR.
a. Write a data word to PORTQS.
b. Establish direction of QSM pins used for I/O by writing to DDRQS.
a. Write a transfer rate value into the BR field.
b. Determine clock phase (CPHA), and clock polarity (CPOL).
c. Determine number of bits to be transferred in a serial operation (BIT).
d. Select master or slave operating mode (MSTR).
e. Enable or disable wired-OR operation (WOMQ).
a. Establish a delay following serial transfer by writing to the DTL field.
b. Establish a delay before serial transfer by writing to the DSCKL field.
a. Write an initial queue pointer value into the NEWQP field.
b. Write a final queue pointer value into the ENDQP field.
c. Enable or disable queue wraparound (WREN).
d. Write wraparound address into the WRTO field.
e. Enable or disable QSPI flag interrupt (SPIFIE).
a. Enable or disable halt at end of queue (HALT).
b. Enable or disable halt and mode fault interrupts (HMIE).
c. Enable or disable loopback (LOOPQ).
a. Write a transfer rate (baud) value into the BR field.
a. Select serial mode (M)
b. Enable use (PE) and type (PT) of parity check.
c. Select use (RWU) and type (WAKE) of receiver wakeup.
d. Enable idle-line detection (ILT) and interrupt (ILIE).
e. Enable or disable wired-OR operation (WOMS).
f. Enable or disable break transmission (BK).
Freescale Semiconductor, Inc.
For More Information On This Product,
QUEUED SERIAL MODULE
Go to: www.freescale.com
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