MC68332GCEH20 Freescale Semiconductor, MC68332GCEH20 Datasheet - Page 56

• Manufacturer Part Number: MC68332GCEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.3.5 Loss of Reference Signal
4-16
During a low-power stop, unless the system clock signal is supplied by an external
source and that source is removed, the SIM clock control logic and the SIM clock sig-
nal (SIMCLK) continue to operate. The periodic interrupt timer and input logic for the
RESET and IRQ pins are clocked by SIMCLK. The SIM can also continue to generate
the CLKOUT signal while in low-power mode.
The stop mode system integration module clock (STSIM) and stop mode external
clock (STEXT) bits in SYNCR determine clock operation during low-power stop. Table
4-9 is a summary of the effects of STSIM and STEXT. MODCLK value is the logic level
on the MODCLK pin during the last reset before LPSTOP execution. Any clock in the
off state is held low. If the synthesizer VCO is turned off during LPSTOP, there is a
PLL relock delay after the VCO is turned back on.
LPSTOP
The state of the reset enable (RSTEN) bit in SYNCR determines what happens when
clock logic detects a reference failure.
The limp status bit (SLIMP) in SYNCR indicates whether the synthesizer has a refer-
ence signal. It is set when a reference failure is detected.
Mode
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
When RSTEN is cleared (default state out of reset), the clock synthesizer is forced
into an operating condition referred to as limp mode. Limp mode frequency varies
from device to device, but maximum limp frequency does not exceed one half max-
imum system clock when X = 0, or maximum system clock frequency when X = 1.
When RSTEN is set, the SIM resets the MCU.
MODCLK
1
1
0
0
0
0
0
1
1
1
Freescale Semiconductor, Inc.
Pins
For More Information On This Product,
Reference
Reference
Reference
Reference
Reference
Crystal or
Crystal or
Crystal or
Crystal or
Crystal or
External
External
External
External
External
SYSTEM INTEGRATION MODULE
EXTAL
Clock
Clock
Clock
Clock
Clock
Table 4-9 Clock Control
Go to: www.freescale.com
STSIM
X
X
0
0
1
1
0
0
1
1
SYNCR Bits
STEXT
X
X
0
1
0
1
0
1
0
1
Reference
Reference
Crystal or
Crystal or
SIMCLK
External
External
External
External
External
Clock
Clock
Clock
Clock
Clock
VCO
VCO
VCO
Clock Status
Reference
CLKOUT
External
External
External
Crystal/
Clock
Clock
Clock
VCO
VCO
Off
Off
Off
Off
USER’S MANUAL
External
External
External
MC68332
ECLK
Clock
Clock
Clock
VCO
VCO
Off
Off
Off
Off
Off