MC68332GCEH20 Freescale Semiconductor, MC68332GCEH20 Datasheet - Page 97

• Manufacturer Part Number: MC68332GCEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68332
USER’S MANUAL
weak internal pull-up drivers for each of the data lines, so that chip-select operation
will be selected by default out of reset. However, the internal pull-up drivers can be
overcome by bus loading effects — to insure a particular configuration out of reset, use
an active device to put the data lines in a known state during reset. The base address
fields in chip-select base address registers CSBAR[0:10] and chip select option regis-
ters CSOR[0:10] have the reset values shown in Table 4-23. The BYTE fields of
CSOR[0:10] have a reset value of “disable”, so that a chip-select signal cannot be as-
serted until the base and option registers are initialized.
Following reset, the MCU fetches initial stack pointer and program counter values from
the exception vector table, beginning at $000000 in supervisor program space. The
CSBOOT chip-select signal is used to select an external boot ROM mapped to a base
address of $000000. In order to do this, the reset values of the fields that control CS-
BOOT must be different from those of other chip select signals.
The MSB of the CSBOOT field in CSPAR0 has a reset value of one, so that chip-select
function is selected by default out of reset. The BYTE field in option register CSORBT
has a reset value of “both bytes” so that the select signal is enabled out of reset. The
LSB value of the CSBOOT field, determined by the logic level of DATA0 during reset,
selects boot ROM port size. When DATA0 is held low during reset, port size is eight
bits. When DATA0 is held high during reset, port size is 16 bits. DATA0 has a weak
internal pull-up driver, so that a 16-bit port will be selected by default out of reset. How-
ever, the internal pull-up driver can be overcome by bus loading effects —to insure a
particular configuration out of reset, use an active device to put DATA0 in a known
state during reset.
The base address field in chip-select base address register boot (CSBARBT) has a
reset value of all zeros, so that when the initial access to address $000000 is made,
an address match occurs, and the CSBOOT signal is asserted. The block size field in
CSBARBT has a reset value of 1 Mbyte. Table 4-24 shows CSBOOT reset values.
Table 4-23 Chip Select Base and Option
Freescale Semiconductor, Inc.
Async/Sync Mode
Upper/Lower Byte
Address Space
For More Information On This Product,
Base Address
Read/Write
Block Size
Autovector
DSACK
Fields
AS/DS
SYSTEM INTEGRATION MODULE
IPL
Register Reset Values
Go to: www.freescale.com
External Interrupt Vector
Asynchronous Mode
No Wait States
Reset Values
CPU Space
Reserved
Any Level
$000000
Disabled
2 Kbyte
AS
4-57