MC68332GCEH20 Freescale Semiconductor, MC68332GCEH20 Datasheet - Page 230

• Manufacturer Part Number: MC68332GCEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D.3 Standby RAM Module with TPU Emulation
D.3.1 TRAMMCR — TPURAM Module Configuration Register
STOP — Stop Control
RASP[1:0] — TPURAM Array Space Field
D.3.2 TRAMTST — TPURAM Test Register
D.3.3 TRAMBAR — TPURAM Base Address and Status Register
ADDR[23:11] — TPURAM Array Base Address
D-16
ADDR
STOP
15
15
23
0
0
Table D-3 is the TPURAM address map. TPURAM responds to both program and data
space accesses. The RASP bit in the TRAMMCR determines whether the processor
must be operating at the supervisor privilege level to access the array. TPURAM con-
trol registers are accessible at the supervisor privilege level only.
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
This bit controls whether the RAM array is in stop mode or normal operation. Reset
state is zero, for normal operation. In stop mode, the array retains its contents, but can-
not be read or written by the CPU.
TRAMTST is used for factory test of the TPURAM module.
These bits specify address lines ADDR[23:11] of the base address of the TPURAM
array when enabled.
RESET:
RESET:
Access
0 = TPURAM array operates normally.
1 = TPURAM array enters low-power stop mode.
0 = TPURAM array is accessible from the supervisor or user privilege level.
1 = TPURAM array is accessible from the supervisor privilege level only.
ADDR
14
14
22
S
S
S
S
0
0
0
ADDR
13
13
21
0
0
0
ADDR
$YFFB00
$YFFB02
$YFFB04
$YFFB06
12
12
20
Address
0
0
0
Freescale Semiconductor, Inc.
ADDR
11
11
19
For More Information On This Product,
0
0
0
Table D-3 TPURAM Address Map
15 8
ADDR
10
10
18
0
0
0
TPURAM BASE ADDRESS AND STATUS REGISTER (TRAMBAR)
Go to: www.freescale.com
TPURAM MODULE CONFIGURATION REGISTER (TRAMMCR)
REGISTER SUMMARY
ADDR
17
9
0
0
9
0
RASP
ADDR
16
8
1
8
0
TPURAM TEST REGISTER (TRAMTST)
ADDR
15
7
7
0
ADDR
14
6
0
NOT USED
ADDR
13
5
0
7 0
ADDR
12
NOT USED
4
0
ADDR
11
3
0
USER’S MANUAL
NOT USED
2
$YFFB00
$YFFB02
$YFFB04
1
MC68332
RAMD
0
0
S
0