MC68332GCEH20 Freescale Semiconductor, MC68332GCEH20 Datasheet - Page 200

• Manufacturer Part Number: MC68332GCEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

A-26
Num
10
11
12
13
1
2
3
4
5
6
7
8
9
Notes:
1. All AC timing is shown with respect to 20% V
2. In formula, n = External SCK rise + External SCK fall time
3. Data can be recognized properly with longer transition times as long as MOSI/MISO signals from external sourc-
es are at valid V
decision point voltages of the data and clock signals can differ, which can corrupt data if slower transition times
are used.
Operating Frequency
Cycle Time
Enable Lead Time
Enable Lag Time
Clock (SCK) High or Low Time
Sequential Transfer Delay
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Slave Access Time
Slave MISO Disable Time
Data Valid (after SCK Edge)
Data Hold Time (Outputs)
Rise Time
Fall Time
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave (Does Not Require Deselect)
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Input
Output
Input
Output
3
3
2
(V
DD
OH
Function
= 5.0 Vdc
/V
OL
Freescale Semiconductor, Inc.
prior to SCK transitioning between valid V
For More Information On This Product,
10%, V
ELECTRICAL CHARACTERISTICS
Table A-9 QSPI Timing
SS
Go to: www.freescale.com
= 0 Vdc, T
Symbol
DD
t
t
qcyc
t
t
f
lead
t
t
t
t
t
t
t
lag
t
dis
t
op
sw
t
ho
t
and 70% V
su
td
hi
ro
fo
a
ri
v
fi
A
= T
L
2 t
to T
2 t
cyc
DD
Min
cyc
DC
DC
17
13
30
20
20
—
—
—
—
—
—
—
—
—
H,
4
4
2
2
2
0
0
0
– 60
levels unless otherwise noted.
200 pF load on all QSPI pins)
– n
OL
and V
255 t
8192
Max
510
128
1/4
1/4
1/2
—
—
—
—
—
—
—
—
—
50
50
—
—
30
30
1
2
2
2
OH
cyc
. Due to process variation, logic
System Clock Frequency
System Clock Frequency
USER’S MANUAL
SCK
Unit
t
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
cyc
cyc
cyc
cyc
cyc
cyc
cyc
s
s
MC68332