MC68332GCEH20 Freescale Semiconductor, MC68332GCEH20 Datasheet - Page 236

• Manufacturer Part Number: MC68332GCEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D.4.6 SCSR — SCI Status Register
TDRE — Transmit Data Register Empty
TC — Transmit Complete
RDRF — Receive Data Register Full
RAF — Receiver Active
IDLE — Idle-Line Detected
OR — Overrun Error
NF — Noise Error Flag
FE — Framing Error
D-22
15
SCSR contains flags that show SCI operating conditions. These flags are cleared ei-
ther by SCI hardware or by a CPU32 read/write sequence. The sequence consists of
reading SCSR, then reading or writing SCDR.
If an internal SCI signal for setting a status bit comes after the CPU32 has read the
asserted status bits, but before the CPU has written or read SCDR, the newly set sta-
tus bit is not cleared. SCSR must be read again with the bit set and SCDR must be
written or read before the status bit is cleared.
A long-word read can consecutively access both SCSR and SCDR. This action clears
receive status flag bits that were set at the time of the read, but does not clear TDRE
or TC flags. Reading either byte of SCSR causes all 16 bits to be accessed, and any
status bit already set in either byte is cleared on a subsequent read or write of register
SCDR.
RESET:
0 = Register TDR still contains data to be sent to the transmit serial shifter.
1 = A new character can now be written to register TDR.
0 = SCI transmitter is busy.
1 = SCI transmitter is idle.
0 = Register RDR is empty or contains previously read data.
1 = Register RDR contains new data.
0 = SCI receiver is idle.
1 = SCI receiver is busy.
0 = SCI receiver did not detect an idle-line condition.
1 = SCI receiver detected an idle-line condition.
0 = RDRF is cleared before new data arrives.
1 = RDRF is not cleared before new data arrives.
0 = No noise detected on the received data
1 = Noise occurred on the received data.
0 = No framing error on the received data
1 = Framing error or break occurred on the received data.
NOT USED
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
REGISTER SUMMARY
9
TDRE
8
1
TC
7
1
RDRF
6
0
RAF
5
0
IDLE
4
0
OR
3
0
USER’S MANUAL
NF
2
0
$YFFC0C
FE
1
0
MC68332
PF
0
0