MC68332GCEH20 Freescale Semiconductor, MC68332GCEH20 Datasheet - Page 244

• Manufacturer Part Number: MC68332GCEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D.5 Time Processor Unit
D.5.1 TPUMCR — TPU Module Configuration Register
STOP — Stop Bit
TCR1P — Timer Count Register 1 Prescaler Control
D-30
STOP
15
0
Table D-5 is the TPU address map. The column labeled “Access” indicates the privi-
lege level at which the CPU must be operating to access the register. A designation of
“S” indicates that supervisor access is required: a designation of “S/U” indicates that
the register can be programmed to the desired privilege level.
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR.
TCR1 is clocked from the output of a prescaler. The prescaler's input is the internal
TPU system clock divided by either 4 or 32, depending on the value of the PSCK bit.
The prescaler divides this input by 1, 2, 4, or 8. Channels using TCR1 have the capa-
bility to resolve down to the TPU system clock divided by 4.
RESET:
0 = TPU operating normally
1 = Internal clocks shut down
14
0
TCR1P
Access
S/U
S/U
S/U
S/U
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
13
0
12
0
TCR2P
Freescale Semiconductor, Inc.
11
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Table D-5 TPU Address Map
EMU
10
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REGISTER SUMMARY
T2CG
9
0
15 8
DEVELOPMENT SUPPORT CONTROL REGISTER (DSCR)
CHANNEL FUNCTION SELECTION REGISTER 0 (CFSR0)
CHANNEL FUNCTION SELECTION REGISTER 1 (CFSR1)
CHANNEL FUNCTION SELECTION REGISTER 2 (CFSR2)
CHANNEL FUNCTION SELECTION REGISTER 3 (CFSR3)
DEVELOPMENT SUPPORT STATUS REGISTER (DSSR)
TPU MODULE CONFIGURATION REGISTER (TPUMCR)
TPU INTERRUPT CONFIGURATION REGISTER (TICR)
DECODED CHANNEL NUMBER REGISTER (DCNR)
CHANNEL INTERRUPT ENABLE REGISTER (CIER)
CHANNEL INTERRUPT STATUS REGISTER (CISR)
STF
HOST SERVICE REQUEST REGISTER 0 (HSRR0)
HOST SERVICE REQUEST REGISTER 1 (HSRR1)
8
0
SERVICE GRANT LATCH REGISTER (SGLR)
TEST CONFIGURATION REGISTER (TCR)
CHANNEL PRIORITY REGISTER 0 (CPR0)
CHANNEL PRIORITY REGISTER 1 (CPR1)
HOST SEQUENCE REGISTER 0 (HSQR0)
HOST SEQUENCE REGISTER 1 (HSQR1)
SUPV
7
1
PSCK
6
0
LINK REGISTER (LR)
5
0
0
7 0
4
0
0
3
0
USER’S MANUAL
0
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MC68332
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