MC68332GCEH20 Freescale Semiconductor, MC68332GCEH20 Datasheet - Page 249

• Manufacturer Part Number: MC68332GCEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

D.5.11 HSQR0 — Host Sequence Register 0
D.5.12 HSQR1 — Host Sequence Register 1
CH[15:0] — Encoded Host Sequence
D.5.13 HSRR0 — Host Service Request Register 0
D.5.14 HSRR1 — Host Service Request Register 1
CH[15:0] — Encoded Type of Host Service
MC68332
USER’S MANUAL
15
15
15
15
0
0
0
0
The host sequence field selects the mode of operation for the time function selected
on a given channel. The meaning of the host sequence bits depends on the time func-
tion specified.
The host service request field selects the type of host service request for the time func-
tion selected on a given channel. The meaning of the host service request bits de-
pends on the time function specified.
A host service request field cleared to %00 signals the host that service is completed
by the microengine on that channel. The host can request service on a channel by writ-
ing the corresponding host service request field to one of three nonzero states. The
CPU should monitor the host service request register until the TPU clears the service
request to %00 before the CPU changes any parameters or issues a new service re-
quest to the channel.
RESET:
RESET:
RESET:
RESET:
CH 15
CH 15
CH 7
CH 7
14
14
14
14
0
0
0
0
13
13
13
13
0
0
0
0
CH 14
CH 14
CH 6
CH 6
12
12
12
12
0
0
0
0
Freescale Semiconductor, Inc.
11
11
11
11
For More Information On This Product,
0
0
0
0
CH 13
CH 13
CH 5
CH 5
10
10
10
10
0
0
0
0
Go to: www.freescale.com
REGISTER SUMMARY
9
0
9
0
9
0
9
0
CH 12
CH 12
CH 4
CH 4
8
0
8
0
8
0
8
0
7
0
7
0
7
0
7
0
CH 11
CH 11
CH 3
CH 3
6
0
6
0
6
0
6
0
5
0
5
0
5
0
5
0
CH 10
CH 10
CH 2
CH 2
4
0
4
0
4
0
4
0
3
0
3
0
3
0
3
0
CH 9
CH 1
CH 9
CH 1
2
0
2
0
2
0
2
0
$YFFE1A
$YFFE14
$YFFE16
$YFFE18
1
0
1
0
1
0
1
0
CH 8
CH 0
CH 8
CH 0
D-35
0
0
0
0
0
0
0
0