MC68332GCEH20 Freescale Semiconductor, MC68332GCEH20 Datasheet - Page 35

• Manufacturer Part Number: MC68332GCEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

MC68332
USER’S MANUAL
$FFFFFF
$7FF000
$FF0000
$
000000
NOTES:
1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector
2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configure register.
3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally.
Y = M111, where M is the state of the MM bit.
base register and the vector offset.
INTERNAL REGISTERS (MM = 0)
INTERNAL REGISTERS (MM = 1)
SUPERVISOR
COMBINED
AND USER
SPACE
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 3-5 Overall Memory Map
Go to: www.freescale.com
OVERVIEW
TPURAM CTL
00EC–00FC
0040–005C
0080–00BC
00C0–00EB
0100–03FC
RESERVED
RESERVED
VECTOR
OFFSET
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028
002C
0030
0034
0038
003C
006C
0064
0068
006C
0070
0074
0078
007C
QSM
TPU
SIM
NUMBER
VECTOR
64–255
16–23
32–47
48–58
59–63
10
11
12
13
14
15
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
$YFF000
$YFFA00
$YFFA80
$YFFB00
$YFFB40
$YFFC00
$YFFE00
$YFFFFF
(RESERVED COPROCESSOR PROTOCOL VIOLATION)
FORMAT ERROR AND UNINITIALIZED INTERRUPT
FORMAT ERROR AND UNINITIALIZED INTERRUPT
TAP INSTRUCTION VECTORS (0–15)
LEVEL 1 INTERRUPT AUTOVECTOR
LEVEL 2 INTERRUPT AUTOVECTOR
LEVEL 3 INTERRUPT AUTOVECTOR
LEVEL 4 INTERRUPT AUTOVECTOR
LEVEL 5 INTERRUPT AUTOVECTOR
LEVEL 6 INTERRUPT AUTOVECTOR
LEVEL 7 INTERRUPT AUTOVECTOR
RESET — INITIAL STACK POINTER
TRAPcc, TRAPV INSTRUCTIONS
(RESERVED, COPROCESSOR)
(UNASSIGNED, RESERVED)
(UNASSIGNED, RESERVED)
CHK, CHK2 INSTRUCTIONS
HARDWARE BREAKPOINT
USER-DEFINED VECTORS
ILLEGAL INSTRUCTION
SPURIOUS INTERRUPT
PRIVILEGE VIOLATION
LINE 1010 EMULATOR
LINE 1111 EMULATOR
RESET — INITIAL PC
ADDRESS ERROR
ZERO DIVISION
EXCEPTION
BUS ERROR
TYPE OF
TRACE
332 S/U COMB MAP
$XX0000
$XX03FC
3-11