MC68332GCEH20 Freescale Semiconductor, MC68332GCEH20 Datasheet - Page 76

• Manufacturer Part Number: MC68332GCEH20
• Description: IC MCU 32BIT 20MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68332GCEH20

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Type: ROMless
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 15
• Ram Memory Size: 2KB
• Cpu Speed: 20MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Data Bus Width: 32 bit
• Data Ram Size: 2 KB
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 16
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

4.5.6.1 Slave (Factory Test) Mode Arbitration
4.5.6.2 Show Cycles
4-36
State changes occur on the next rising edge of CLKOUT after the internal signal is val-
id. The BG signal transitions on the falling edge of the clock after a state is reached
during which G changes. The bus control signals (controlled by T) are driven by the
MCU immediately following a state change, when bus mastership is returned to the
MCU. State 0, in which G and T are both negated, is the state of the bus arbiter while
the MCU is bus master. Request R and acknowledge A keep the arbiter in state 0 as
long as they are both negated.
This mode is used for factory production testing of internal modules. It is not supported
as a user operating mode. Slave mode is enabled by holding DATA11 low during re-
set. In slave mode, when BG is asserted, the MCU is slaved to an external master that
has full access to all internal registers.
The MCU normally performs internal data transfers without affecting the external bus,
but it is possible to show these transfers during debugging. AS is not asserted exter-
nally during show cycles.
RE-ARBITRATE OR RESUME PROCESSOR
1) ASSERT BUS GRANT (BG)
1) NEGATE BG (AND WAIT FOR
Figure 4-14 Bus Arbitration Flowchart for Single Request
BGACK TO BE NEGATED)
GRANT BUS ARBITRATION
TERMINATE ARBITRATION
OPERATION
Freescale Semiconductor, Inc.
MCU
For More Information On This Product,
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
1) EXTERNAL ARBITRATION DETERMINES
2) NEXT BUS MASTER WAITS FOR BGACK
3) NEXT BUS MASTER ASSERTS BGACK
4) BUS MASTER NEGATES BR
1) PERFORM DATA TRANSFERS (READ AND
1) NEGATE BGACK
1) ASSERT BUS REQUEST (BR)
NEXT BUS MASTER
TO BE NEGATED
TO BECOME NEW MASTER
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES
ACKNOWLEDGE BUS MASTERSHIP
RELEASE BUS MASTERSHIP
OPERATE AS BUS MASTER
REQUESTING DEVICE
REQUEST THE BUS
BUS ARB FLOW
USER’S MANUAL
MC68332