PIC16LF723A-I/ML Microchip Technology, PIC16LF723A-I/ML Datasheet - Page 101

• Manufacturer Part Number: PIC16LF723A-I/ML
• Description: MCU PIC 3.5K FLASH XLP 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 25
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 11-1:
TABLE 11-1:
 2010 Microchip Technology Inc.
CPSCON0
INTCON
OPTION_REG
TMR0
TRISA
Legend:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/W-1
RBPU
Name
– = Un implemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
Timer0 Module Register
CPSON
TRISA7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual PORT latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin or CPSOSC signal
0 = Internal instruction cycle clock (F
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
RBPU
Bit 7
GIE
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
INTEDG
R/W-1
OPTION_REG: OPTION REGISTER
INTEDG
TRISA6
PEIE
B
Bit 6
—
IT
000
001
010
011
100
101
110
111
V
W = Writable bit
‘1’ = Bit is set
ALUE
R/W-1
T0CS
TRISA5
T0CS
Bit 5
T0IE
—
TMR0 R
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
TRISA4
T0SE
ATE
Bit 4
INTE
—
R/W-1
T0SE
WDT R
CPSRNG1 CPSRNG0
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
OSC
TRISA3
RBIE
Bit 3
PSA
/4)
ATE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PIC16F/LF722A/723A
R/W-1
PSA
TRISA2
Bit 2
T0IF
PS2
CPSOUT
TRISA1
Bit 1
INTF
PS1
R/W-1
PS2
TRISA0
T0XCS
RBIF
Bit 0
PS0
x = Bit is unknown
R/W-1
0--- 0000
0000 000x
1111 1111
xxxx xxxx
1111 1111
POR, BOR
PS1
Value on
DS41417A-page 101
0--- 0000
0000 000x
1111 1111
uuuu uuuu
1111 1111
R/W-1
Value on
all other
PS0
Resets
bit 0