PIC16LF723A-I/ML Microchip Technology, PIC16LF723A-I/ML Datasheet - Page 122

• Manufacturer Part Number: PIC16LF723A-I/ML
• Description: MCU PIC 3.5K FLASH XLP 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 25
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F/LF722A/723A
REGISTER 14-2:
TABLE 14-2:
DS41417A-page 122
ANSELA
ANSELB
OPTION_REG
PIE1
PIR1
T1CON
T2CON
TRISA
TRISB
Legend:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-3
bit 2-0
Name
U-0
—
- = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the capacitive sensing module.
TMR1CS1
TMR1GIE
TMR1GIF
TRISA7
TRISB7
RBPU
Bit 7
Unimplemented: Read as ‘0’
CPSCH<2:0>: Capacitive Sensing Channel Select bits
If CPSON = 0:
If CPSON = 1:
—
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING
These bits are ignored. No channel is selected.
U-0
0000 = channel 0, (CPS0)
0001 = channel 1, (CPS1)
0010 = channel 2, (CPS2)
0011 = channel 3, (CPS3)
0100 = channel 4, (CPS4)
0101 = channel 5, (CPS5)
0110 = channel 6, (CPS6)
0111 = channel 7, (CPS7)
—
CPSCON1: CAPACITIVE SENSING CONTROL REGISTER 1
TMR1CS0
TOUTPS3
INTEDG
TRISA6
TRISB6
ADIE
ADIF
Bit 6
—
—
W = Writable bit
‘1’ = Bit is set
TOUTPS2
T1CKPS1
TRISA5
TRISB5
ANSA5
ANSB5
T0CS
U-0
RCIE
RCIF
Bit 5
—
TOUTPS1
T1CKPS0
TRISA4
TRISB4
ANSA4
ANSB4
T0SE
Bit 4
TXIE
TXIF
U-0
—
T1OSCEN
TOUTPS0
TRISA3
TRISB3
ANSA3
ANSB3
SSPIE
SSPIF
Bit 3
PSA
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
TMR2ON
T1SYNC
CCP1IE
CCP1IF
TRISA2
TRISB2
ANSA2
ANSB2
Bit 2
PS2
T2CKPS1
TMR2IE
TMR2IF
TRISA1
TRISB1
ANSA1
ANSB1
CPSCH2
Bit 1
PS1
R/W-0
—
T2CKPS0
TMR1ON
TMR1IE
TMR1IF
TRISA0
TRISB0
ANSA0
ANSB0
Bit 0
 2010 Microchip Technology Inc.
PS0
x = Bit is unknown
CPSCH1
R/W-0
--11 1111
--11 1111
1111 1111
0000 0000
0000 0000
0000 00-0
-000 0000
1111 1111
1111 1111
POR, BOR
Value on
CPSCH0
--11 1111
--11 1111
1111 1111
0000 0000
0000 0000
0000 00-0
-000 0000
1111 1111
1111 1111
R/W-0
Value on
all other
Resets
bit 0