PIC16LF723A-I/ML Microchip Technology, PIC16LF723A-I/ML Datasheet - Page 172

• Manufacturer Part Number: PIC16LF723A-I/ML
• Description: MCU PIC 3.5K FLASH XLP 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 25
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F/LF722A/723A
17.2.7
During any SCL low phase, any device on the I
may hold the SCL line low and delay, or pause, the
transmission of data. This “stretching” of a transmission
allows devices to slow down communication on the
bus. The SCL line must be constantly sampled by the
master to ensure that all devices on the bus have
released SCL for more data.
Stretching usually occurs after an ACK bit of a
transmission, delaying the first bit of the next byte. The
SSP module hardware automatically stretches for two
conditions:
• After a 10-bit address byte is received (update
• Anytime the CKP bit of the SSPCON register is
The module will hold SCL low until the CKP bit is set.
This allows the user slave software to update SSPBUF
with data that may not be readily available. In 10-bit
addressing modes, the SSPADD register must be
updated after receiving the first and second address
bytes. The SSP module will hold the SCL line low until
the SSPADD has a byte written to it. The UA bit of the
SSPSTAT register will be set, along with SSPIF,
indicating an address update is needed.
17.2.8
Master mode of operation is supported in firmware
using interrupt generation on the detection of the Start
and Stop conditions. The Stop (P) and Start (S) bits of
the SSPSTAT register are cleared from a Reset or
when the SSP module is disabled (SSPEN cleared).
The Stop (P) and Start (S) bits will toggle based on the
Start and Stop conditions. Control of the I
be taken when the P bit is set or the bus is Idle and both
the S and P bits are clear.
In Firmware Master mode, the SCL and SDA lines are
manipulated by setting/clearing the corresponding TRIS
bit(s). The output level is always low, irrespective of the
value(s) in the corresponding PORT register bit(s).
When transmitting a ‘1’, the TRIS bit must be set (input)
and a ‘0’, the TRIS bit must be clear (output).
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt will occur if
enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
Firmware Master mode of operation can be done with
either the Slave mode Idle (SSPM<3:0> = 1011), or
with either of the Slave modes in which interrupts are
enabled. When both master and slave functionality is
enabled, the software needs to differentiate the
source(s) of the interrupt.
DS41417A-page 172
SSPADD register)
cleared by hardware
CLOCK STRETCHING
FIRMWARE MASTER MODE
2
C bus may
2
C bus
Refer
Implementation of I
information.
17.2.9
In Multi-Master mode, the interrupt generation on the
detection of the Start and Stop conditions allow the
determination of when the bus is free. The Stop (P) and
Start (S) bits are cleared from a Reset or when the SSP
module is disabled. The Stop (P) and Start (S) bits will
toggle based on the Start and Stop conditions. Control
of the I
SSPSTAT register is set or when the bus is Idle, and
both the S and P bits are clear. When the bus is busy,
enabling the SSP Interrupt will generate the interrupt
when the Stop condition occurs.
In Multi-Master operation, the SDA line must be
monitored to see if the signal level is the expected
output level. This check only needs to be done when a
high level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRIS bits). There are two stages
where this arbitration of the bus can be lost. They are
the address transfer and data transfer stages.
When the slave logic is enabled, the slave continues to
receive. If arbitration was lost during the address
transfer stage, communication to the device may be in
progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data
transfer stage, the device will need to re-transfer the
data at a later time.
Refer to Application Note AN578, “Use of the SSP
Module in the I
(DS00578) for more information.
2
to
C bus may be taken when the P bit of the
MULTI-MASTER MODE
Application
2
C™ Bus Master” (DS00554) for more
2
C™ Multi-Master Environment”
 2010 Microchip Technology Inc.
Note
AN554,
“Software