PIC16LF723A-I/ML Microchip Technology, PIC16LF723A-I/ML Datasheet - Page 44

• Manufacturer Part Number: PIC16LF723A-I/ML
• Description: MCU PIC 3.5K FLASH XLP 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 25
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F/LF722A/723A
4.5.5
The PIR2 register contains the interrupt flag bits, as
shown in Register 4-5.
REGISTER 4-5:
TABLE 4-1:
DS41417A-page 44
INTCON
OPTION_REG
PIE1
PIE2
PIR1
PIR2
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture,
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-1
bit 0
Note:
Name
U-0
—
Compare and PWM.
PIR2 REGISTER
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
TMR1GIE
TMR1GIF
Unimplemented: Read as ‘0’
CCP2IF: CCP2 Interrupt Flag bit
Capture Mode:
Compare Mode:
PWM mode:
Unused in this mode
RBPU
Bit 7
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
GIE
—
—
software
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
U-0
—
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
INTEDG
ADIE
ADIF
Bit 6
PEIE
—
—
should
W = Writable bit
‘1’ = Bit is set
U-0
—
T0CS
RCIE
RCIF
Bit 5
T0IE
—
—
ensure
T0SE
INTE
TXIE
TXIF
Bit 4
—
—
U-0
the
—
SSPIE
SSPIF
RBIE
Bit 3
PSA
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
—
CCP1IE
CCP1IF
Bit 2
T0IF
PS2
—
—
TMR2IE
TMR2IF
Bit 1
INTF
PS1
—
—
U-0
—
TMR1IE 0000 0000 0000 0000
CCP2IE ---- ---0 ---- ---0
TMR1IF 0000 0000 0000 0000
CCP2IF ---- ---0 ---- ---0
RBIF
Bit 0
PS0
 2010 Microchip Technology Inc.
x = Bit is unknown
U-0
0000 000x 0000 000x
1111 1111 1111 1111
—
POR, BOR
Value on
CCP2IF
R/W-0
Value on
all other
Resets
bit 0