PIC16LF723A-I/ML Microchip Technology, PIC16LF723A-I/ML Datasheet - Page 20

• Manufacturer Part Number: PIC16LF723A-I/ML
• Description: MCU PIC 3.5K FLASH XLP 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 25
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F/LF722A/723A
TABLE 2-1:
DS41417A-page 20
80h
81h
82h
83h
84h
85h
86h
87h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
Address
Bank 1
(2)
(2)
(2)
(2)
(1, 2)
(2)
1:
2:
3:
4:
5:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
T1GCON
OSCCON
OSCTUNE
PR2
SSPADD
SSPMSK
SSPSTAT
WPUB
IOCB
TXSTA
SPBRG
APFCON
FVRCON
ADCON1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
Accessible only when SSPM<3:0> = 1001.
Accessible only when SSPM<3:0>  1001.
This bit is always ‘1’ as RE3 is input only.
Name
—
—
—
—
(4)
(3)
PIC16F/LF722A/723A SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Timer2 Period Register
Synchronous Serial Port (I
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Unimplemented
TMR1GIE
TMR1GE
FVRRDY
TRISA7
TRISB7
TRISC7
WPUB7
IOCB7
RBPU
CSRC
BRG7
Bit 7
SMP
GIE
IRP
—
—
—
—
—
—
—
—
T1GPOL
INTEDG
TRISA6
TRISB6
TRISC6
WPUB6
FVREN
ADCS2
IOCB6
BRG6
PEIE
ADIE
Bit 6
RP1
CKE
TX9
—
—
—
—
—
—
—
TRISC5
WPUB5
TRISA5
TRISB5
T1GTM
2
2
ADCS1
IRCF1
IOCB5
BRG5
T0CS
TUN5
TXEN
RCIE
C
C
Bit 5
T0IE
RP0
D/A
—
—
—
—
™
™
—
—
mode) Address Register
mode) Address Mask Register
Write Buffer for the upper 5 bits of the Program Counter
T1GSPM
TRISA4
TRISB4
TRISC4
WPUB4
ADCS0
IRCF0
IOCB4
SYNC
BRG4
TUN4
T0SE
Bit 4
INTE
TXIE
TO
—
—
—
—
—
P
TRISE3
T1GGO/
TRISA3
TRISB3
TRISC3
WPUB3
SSPIE
DONE
IOCB3
BRG3
TUN3
RBIE
ICSL
Bit 3
PSA
PD
—
—
—
—
—
—
S
(5)
CCP1IE
T1GVAL
TRISA2
TRISB2
TRISC2
WPUB2
IOCB2
BRGH
BRG2
TUN2
ICSS
Bit 2
T0IF
PS2
R/W
—
—
—
—
—
—
Z
T1GSS1
ADFVR1
ADREF1
TMR2IE
TRISA1
TRISB1
TRISC1
WPUB1
SSSEL
IOCB1
TUN1
TRMT
BRG1
Bit 1
INTF
POR
PS1
DC
UA
—
—
—
 2010 Microchip Technology Inc.
CCP2SEL ---- --00
ADFVR0
ADREF0
T1GSS0
TRISA0
TRISB0
TRISC0
TMR1IE
CCP2IE
WPUB0
IOCB0
TUN0
BRG0
TX9D
Bit 0
RBIF
BOR
PS0
BF
—
—
C
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
1111 1111
1111 1111
---- 1111
---0 0000
0000 000x
0000 0000
---- ---0
---- --qq
0000 0x00
--10 qq--
--00 0000
1111 1111
0000 0000
1111 1111
0000 0000
1111 1111
0000 0000
0000 -010
0000 0000
q0-- --00
0000 --00
POR, BOR
Value on:
—
—
—
—
113,35
115,35
165,35
176,35
163,35
142,35
144,35
26,34
23,35
25,34
22,34
26,34
48,35
57,35
67,35
74,35
25,34
40,34
41,35
42,35
24,35
79,35
80,35
57,35
58,35
47,35
97,35
93,35
Page
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—
—
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