PIC16LF723A-I/ML Microchip Technology, PIC16LF723A-I/ML Datasheet - Page 144

• Manufacturer Part Number: PIC16LF723A-I/ML
• Description: MCU PIC 3.5K FLASH XLP 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 25
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F/LF722A/723A
16.2
The Baud Rate Generator (BRG) is an 8-bit timer that
is dedicated to the support of both the asynchronous
and synchronous AUSART operation.
The SPBRG register determines the period of the free
running baud rate timer. In Asynchronous mode the
multiplier of the baud rate period is determined by the
BRGH bit of the TXSTA register. In Synchronous mode,
the BRGH bit is ignored.
Table 16-3 contains the formulas for determining the
baud rate. Example 16-1 provides a sample calculation
for determining the baud rate and baud rate error.
Typical baud rates and error values for various
asynchronous modes have been computed for your
convenience and are shown in Table 16-3. It may be
advantageous to use the high baud rate (BRGH = 1), to
reduce the baud rate error.
Writing a new value to the SPBRG register causes the
BRG timer to be reset (or cleared). This ensures that
the BRG does not wait for a timer overflow before
outputting the new baud rate.
TABLE 16-3:
TABLE 16-4:
DS41417A-page 144
Legend:
RCSTA
SPBRG
TXSTA
Legend:
Name
SYNC
0
0
1
AUSART Baud Rate Generator
(BRG)
Configuration Bits
x = Don’t care, n = value of SPBRG register
x = unknown, - = unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator.
SPEN
BRG7
CSRC
Bit 7
BAUD RATE FORMULAS
REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR
BRG6
Bit 6
BRGH
RX9
TX9
0
1
x
SREN
BRG5
TXEN
Bit 5
CREN
BRG4
SYNC
Bit 4
AUSART Mode
Asynchronous
Asynchronous
Synchronous
ADDEN
BRG3
Bit 3
—
BRG2
BRGH
FERR
EXAMPLE 16-1:
Bit 2
For a device with F
9600, and Asynchronous mode with SYNC = 0 and BRGH
= 0 (as seen in Table 16-3):
Solving for SPBRG:
%
Desired Baud Rate
Error
Actual Baud Rate
OERR
TRMT
BRG1
Bit 1
=
=
SPBRG




Actual Baud Rate Desired Baud Rate
------------------------------------------------------------------------------------------------- -
9615 9600
----------------------------- -
9600
OSC
–
RX9D
BRG0
TX9D
Bit 0
=
=
=
=
=
=
CALCULATING BAUD
RATE ERROR
Desired Baud Rate

-------------------------- -
64 25
9615
of 16 MHz, desired baud rate of
-------------------------------------- -
64 SPBRG




 2010 Microchip Technology Inc.
16000000
25.042
-------------------------------------------------------- -
64 Desired Baud Rate
16000000
----------------------- -
64
Baud Rate Formula




100


F
F
F
9600
F
OSC
OSC
0000 000x
0000 0000
0000 -010
OSC
POR, BOR
+
OS C
Value on

=
–
1
=
/[64 (n+1)]
/[16 (n+1)]
F


/[4 (n+1)]
0.16%


OS C
+
25
–
1
1

0000 000x
0000 0000
0000 -010

Value on
all other


Resets
–
1


100