PIC16LF723A-I/ML Microchip Technology, PIC16LF723A-I/ML Datasheet - Page 89

• Manufacturer Part Number: PIC16LF723A-I/ML
• Description: MCU PIC 3.5K FLASH XLP 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 25
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 9-1:
FIGURE 9-2:
 2010 Microchip Technology Inc.
Legend: Shaded cells are outside of recommended range.
Note 1:
Clock Source
Fosc/16
Fosc/32
Fosc/64
ADC Clock Period (T
Fosc/2
Fosc/4
Fosc/8
ADC
F
2:
3:
4:
RC
Tcy to T
The F
These values violate the minimum required T
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the F
conversion will be performed during Sleep.
Set GO/DONE bit
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
AD
RC
T
ADC CLOCK PERIOD (T
AD
source has a typical T
ADCS<2:0>
0
ANALOG-TO-DIGITAL CONVERSION T
Conversion Starts
000
100
001
101
010
110
x11
T
AD
AD
)
1
T
AD
b7
1.0-6.0 s
2
100 ns
200 ns
400 ns
20 MHz
800 ns
1.6 s
3.2 s
AD
T
time of 1.6 s for V
AD
b6
AD
(2)
(2)
(2)
(1,4)
3
) V
S
T
1.0-6.0 s
. DEVICE OPERATING FREQUENCIES
AD
b5
125 ns
250 ns
0.5 s
AD
16 MHz
4
1.0 s
2.0 s
4.0 s
time.
T
PIC16F/LF722A/723A
(2)
(2)
(2)
Device Frequency (F
AD
ADRES register is loaded,
GO/DONE bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input
b4
(1,4)
DD
5
.
RC
AD
1.0-6.0 s
clock source is only recommended if the
T
CYCLES
250 ns
500 ns
AD
b3
8.0 s
8 MHz
1.0 s
2.0 s
4.0 s
6
(3)
(2)
(2)
(1,4)
T
AD
b2
7
OSC
1.0-6.0 s
16.0 s
500 ns
T
8.0 s
)
4 MHz
AD
1.0 s
2.0 s
4.0 s
b1
8
(3)
(2)
(3)
(1,4)
T
AD
b0
DS41417A-page 89
9
1.0-6.0 s
16.0 s
32.0 s
64.0 s
8.0 s
1 MHz
2.0 s
4.0 s
(3)
(3)
(3)
(3)
(1,4)