PIC16LF723A-I/ML Microchip Technology, PIC16LF723A-I/ML Datasheet - Page 103

• Manufacturer Part Number: PIC16LF723A-I/ML
• Description: MCU PIC 3.5K FLASH XLP 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 25
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

12.0
The Timer1 module is a 16-bit timer/counter with the
following features:
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 3-bit prescaler
• Dedicated LP oscillator circuit
• Synchronous or asynchronous operation
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP)
FIGURE 12-1:
 2010 Microchip Technology Inc.
Asynchronous mode only)
From WDT
Overflow
From Timer2
T1G
From Timer0
Match PR2
Overflow
T1GSS<1:0>
Note 1: ST Buffer is high speed type when using T1CKI.
TIMER1 MODULE WITH GATE
CONTROL
T1OSO/T1CKI
T1OSCEN
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
T1GPOL
T1CKI
T1OSI
Set flag bit
TMR1IF on
Overflow
00
10
11
TIMER1 BLOCK DIAGRAM
01
TMR1ON
T1GTM
T1OSC
TMR1H
EN
OUT
TMR1
(1)
T1G_IN
(2)
D
R
CK
TMR1L
Q
Q
1
0
TMR1CS<1:0>
Cap. Sensing
0
1
Oscillator
T1GGO/DONE
Q
Internal
Internal
F
OSC
Clock
Clock
F
OSC
EN
/4
D
PIC16F/LF722A/723A
• Selectable Gate Source Polarity
• Gate Toggle Mode
• Gate Single-pulse Mode
• Gate Value Status
• Gate Event Interrupt
Figure 12-1 is a block diagram of the Timer1 module.
Single Pulse
Acq. Control
11
10
01
00
T1CLK
T1GSPM
T1CKPS<1:0>
T1SYNC
Prescaler
1, 2, 4, 8
TMR1ON
0
1
2
0
1
Internal
F
Clock
T1GVAL
OSC
TMR1GE
/2
Q1
Synchronized
Synchronize
Interrupt
Clock Input
D
EN
det
det
Sleep Input
Q
(3)
DS41417A-page 103
Set
TMR1GIF
T1GCON
Data Bus
RD