PIC16LF723A-I/ML Microchip Technology, PIC16LF723A-I/ML Datasheet - Page 21

• Manufacturer Part Number: PIC16LF723A-I/ML
• Description: MCU PIC 3.5K FLASH XLP 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 25
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 2-1:
 2010 Microchip Technology Inc.
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
180h
181h
182h
183h
184h
185h
186h
187h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
Legend:
Note
Address
Bank 2
Bank 3
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1, 2)
(2)
(1, 2)
(2)
1:
2:
3:
4:
5:
INDF
TMR0
PCL
STATUS
FSR
CPSCON0
CPSCON1
PCLATH
INTCON
PMDATL
PMADRL
PMDATH
PMADRH
INDF
OPTION_REG
PCL
STATUS
FSR
ANSELA
ANSELB
PCLATH
INTCON
PMCON1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
Accessible only when SSPM<3:0> = 1001.
Accessible only when SSPM<3:0>  1001.
This bit is always ‘1’ as RE3 is input only.
Name
—
—
—
—
—
—
—
PIC16F/LF722A/723A SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module Register
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Program Memory Read Data Register Low Byte
Program Memory Read Address Register Low Byte
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Reserved
CPSON
RBPU
Bit 7
IRP
GIE
IRP
GIE
—
—
—
—
—
—
—
INTEDG
PEIE
PEIE
Bit 6
RP1
RP1
—
—
—
—
—
—
—
—
—
Program Memory Read Data Register High Byte
ANSA5
ANSB5
T0CS
Bit 5
T0IE
T0IE
RP0
RP0
—
—
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
Program Memory Read Address Register High Byte
Write Buffer for the upper 5 bits of the Program Counter
ANSA4
ANSB4
T0SE
Bit 4
INTE
INTE
TO
TO
—
—
—
CPSRNG1 CPSRNG0
CPSCH3
ANSA3
ANSB3
PIC16F/LF722A/723A
RBIE
RBIE
Bit 3
PSA
PD
PD
—
CPSCH2
ANSA2
ANSB2
Bit 2
T0IF
T0IF
PS2
—
Z
Z
CPSOUT
CPSCH1
ANSA1
ANSB1
INTF
INTF
Bit 1
PS1
DC
DC
—
CPSCH0
ANSA0
ANSB0
T0XCS
RBIF
RBIF
Bit 0
PS0
RD
C
C
DS41417A-page 21
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
0--- 0000
---- 0000
---0 0000
0000 000x
xxxx xxxx
xxxx xxxx
--xx xxxx
---x xxxx
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
--11 1111
--11 1111
---0 0000
0000 000x
1--- ---0
POR, BOR
Value on:
—
—
—
—
—
—
—
121,35
122,35
177,35
177,35
177,35
177,35
178,35
26,34
99,34
25,34
22,34
26,34
25,34
40,34
26,34
23,35
25,34
22,34
26,34
49,35
58,35
25,34
40,34
Page
—
—
—
—
—
—
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