PIC16LF723A-I/ML Microchip Technology, PIC16LF723A-I/ML Datasheet - Page 29

• Manufacturer Part Number: PIC16LF723A-I/ML
• Description: MCU PIC 3.5K FLASH XLP 28-QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF723A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 25
• Program Memory Type: FLASH
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16LF
• No. Of I/o's: 25
• Ram Memory Size: 192Byte
• Cpu Speed: 20MHz
• No. Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

3.1
The PIC16F/LF722A/723A has a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a Reset does not drive the
MCLR pin low.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to V
network, as shown in Figure 3-2, is suggested.
An internal MCLR option is enabled by clearing the
MCLRE bit in the Configuration Word register. When
MCLRE = 0, the Reset signal to the chip is generated
internally. When the MCLRE = 1, the RE3/MCLR pin
becomes an external Reset input. In this mode, the
RE3/MCLR pin has a weak pull-up to V
Serial Programming is not affected by selecting the
internal MCLR option.
FIGURE 3-2:
3.2
The on-chip POR circuit holds the chip in Reset until V
has reached a high enough level for proper operation. A
maximum rise time for V
Section 23.0 “Electrical Specifications” for details. If
the BOR is enabled, the maximum rise time specification
does not apply. The BOR circuitry will keep the device in
Reset until V
“Brown-Out Reset (BOR)”).
When the device starts normal operation (exits the
Reset condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
 2010 Microchip Technology Inc.
V
DD
MCLR
Power-on Reset (POR)
R1
10 k
C1
0.1 F
DD
reaches V
RECOMMENDED MCLR
CIRCUIT
DD
BOR
DD
MCLR
. The use of an RC
is required. See
(see Section 3.5
PIC
®
MCU
DD
. In-Circuit
DD
PIC16F/LF722A/723A
3.3
The Power-up Timer provides a fixed 64 ms (nominal)
time-out on power-up only, from POR or Brown-out
Reset. The Power-up Timer operates from the WDT
oscillator. For more information, see Section 7.3
“Internal Clock Modes”. The chip is kept in Reset as
long as PWRT is active. The PWRT delay allows the
V
PWRTE, can disable (if set) or enable (if cleared or pro-
grammed) the Power-up Timer. The Power-up Timer
should be enabled when Brown-out Reset is enabled,
although it is not required.
The Power-up Timer delay will vary from chip-to-chip
and vary due to:
• V
• Temperature variation
• Process variation
See
“Electrical Specifications”).
3.4
The WDT has the following features:
• Shares an 8-bit prescaler with Timer0
• Time-out period is from 17 ms to 2.2 seconds,
• Enabled by a Configuration bit
WDT is cleared under certain conditions described in
Table 3-1.
3.4.1
The WDT derives its time base from 31 kHz internal
oscillator.
DD
Note:
nominal
Note:
DD
to rise to an acceptable level. A Configuration bit,
DC
variation
Power-up Timer (PWRT)
Watchdog Timer (WDT)
The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word.
WDT OSCILLATOR
When the Oscillator Start-up Timer (OST)
is invoked, the WDT is held in Reset,
because the WDT Ripple Counter is used
by the OST to perform the oscillator delay
count. When the OST count has expired,
the WDT will begin counting (if enabled).
parameters
for
details
DS41417A-page 29
(Section 23.0