ST7FLITE35F2M6 STMicroelectronics, ST7FLITE35F2M6 Datasheet - Page 172

• Manufacturer Part Number: ST7FLITE35F2M6
• Description: IC MCU 8BIT 8K FLASH 20SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE35F2M6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7FLITE3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: LINSCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5085 - EVAL BOARD UNIV MOTOR CONTROL497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Function Descriptions
Table 116. LART_Disable
Notes: If PWM output is disabled, the Output compare mode is enabled as the OE bit is
172/235
Function Name
Function Prototype
Behaviour Description
Input Parameter
Output Parameters
Required Preconditions
Functions called
Postconditions
See also
cleared.
1) Feature available only for ST7FLite1, ST7FLite2, ST7FLite3 and ST7DALI devices.
2) Feature available only on ST7FLite3 device.
LART_Disable
Void LART_Disable(Lart_Disable_Param DValue)
Disables overflow interrupt or compare interrupt or makes
counter clock OFF or all of these depending upon the input
parameter passed. More than one input parameter can be
passed by logically ORing them together.
LART_OVF_IT_DISABLE
disables overflow interrupt
LART_OCMP_IT_DISABLE
disables compare interrupt
LART_COUNTER_CLK_OFF
counter clock OFF
LART_PWM_DISABLE
disables PWM0 output
LART_PWM0_DISABLE
disables PWM0 output
LART_PWM1_DISABLE
disables PWM1 output
LART_PWM2_DISABLE
disables PWM2 output
LART_PWM3_DISABLE
disables PWM3 output
LART_ICAP_IT_DISABLE
disables Input Capture interrupt
LART_CTR2_DISABLE
disables counter 2, uses counter 1 only
LART_OVF2_IT_DISABLE
disables counter 2 overflow interrupt
LART_LONG_ICAP_DISABLE
disables long input capture mode
None
Interrupts enabled or counter clock selected
None
Overflow interrupt or compare interrupt or counter clock is
OFF depending upon the input parameter passed.
LART_Init
2)
1)
1)
1)
1)
2)
2)