R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 125

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 12.3
12.1.6
Interrupt Control Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
1.
2.
The following describes enabling and disabling the maskable interrupts and setting the priority for
acknowledgement. The explanation does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and bits ILVL2 to ILVL0 in each interrupt control register to enable or
disable maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control
register.
Figure 12.3 shows the Interrupt Control Register, Figure 12.4 shows Registers TRD0IC, TRD1IC, SSUIC, and
IICIC and Figure 12.5 shows the INTiIC Register.
Only 0 can be w ritten to the IR bit. Do not w rite 1.
Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents .
Feb 29, 2008
Interrupt Control
Interrupt Control Register
Bit Symbol
(b7-b4)
Page 106 of 485
ILVL0
ILVL1
ILVL2
(2)
TREIC
KUPIC
ADIC
S0TIC
S0RIC
S1TIC
S1RIC
TRAIC
TRBIC
—
IR
Symbol
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Bit Name
Address
004Ah
004Dh
004Eh
0051h
0052h
0053h
0054h
0056h
0058h
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Requests no interrupt
1 : Requests interrupt
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
After Reset
Function
12. Interrupts
RW
RW
RW
RW
RW
—
(1)