R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 246

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Table 14.29
j = either A, B, C, or D
Count sources
Count operations
PWM waveform
Count start condition
Count stop conditions
Interrupt request generation
timing
TRDIOA0 pin function
TRDIOB0 pin function
TRDIOD0 pin function
TRDIOA1 pin function
TRDIOC1 pin function
TRDIOB1 pin function
TRDIOD1 pin function
TRDIOC0 pin function
INT0 pin function
Read from timer
Write to timer
Select functions
Feb 29, 2008
Reset Synchronous PWM Mode Specifications
Item
Page 227 of 485
f1, f2, f4, f8, f32, fOCO40M
External signal input to the TRDCLK pin (valid edge selected by a
program)
The TRD0 register is incremented (the TRD1 register is not used).
PWM period
Active level width of normal-phase : 1/fk × (m-n)
Active level width of counter-phase: 1/fk × (n+1)
1 (count starts) is written to the TSTART0 bit in the TRDSTR register.
• 0 (count stops) is written to the TSTART0 bit in the TRDSTR register
• When the CSEL0 bit in the TRDSTR register is set to 0, the count
• Compare match (the content of the TRD0 register matches content
• The TRD0 register overflows
Programmable I/O port or TRDCLK (external clock) input
PWM1 output normal-phase output
PWM1 output counter-phase output
PWM2 output normal-phase output
PWM2 output counter-phase output
PWM3 output normal-phase output
PWM3 output counter-phase output
Output inverted every PWM period
Programmable I/O port, pulse output forced cutoff signal input, or
INT0 interrupt input
The count value can be read by reading the TRD0 register.
The value can be written to the TRD0 register.
• The active level of normal-phase and counter-phase and initial
• Buffer operation (Refer to 14.3.2 Buffer Operation.)
• Pulse output forced cutoff signal input (Refer to 14.3.4 Pulse
when the CSEL0 bit in the TRDSTR register is set to 1.
stops at the compare match in the TRDGRA0 register.
of registers TRDGRj0, TRDGRA1, and TRDGRB1).
output level selected individually.
Output Forced Cutoff.)
fk: Frequency of count source
m: Value set in the TRDGRA0 register
n: Value set in the TRDGRB0 register (PWM1 output),
The PWM output pin holds output level before the count stops
The PWM output pin holds level after output change at compare
match.
Counter-phase
Normal-phase
Value set in the TRDGRA1 register (PWM2 output),
Value set in the TRDGRB1 register (PWM3 output)
n+1
m+1
Specification
m-n
: 1/fk × (m+1)
(When “L” is selected as the active level)
14. Timers