R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 85

IC R8C/25 MCU FLASH 52LQFP

R5F21257SNFP#U0

Manufacturer Part Number
R5F21257SNFP#U0
Description
IC R8C/25 MCU FLASH 52LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/25r
Datasheets

Specifications of R5F21257SNFP#U0

Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
52-LQFP
For Use With
R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Manufacturer:
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Quantity:
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Manufacturer:
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Quantity:
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Company:
Part Number:
R5F21257SNFP#U0R5F21257SNFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Table 7.31
X: 0 or 1
NOTES:
Table 7.32
X: 0 or 1
NOTES:
Table 7.33
X: 0 or 1
NOTE:
Table 7.34
Register
Setting
Register
Register
Register
Value
Setting
Setting
Setting
Value
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
Value
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
2. N-channel open drain output by setting the CSOS bit in the SSMR2 register to 1 when this pin functions as output.
Value
1. Pulled up by setting the PU07 bit in the PUR0 register to 1.
Bit
Bit
Bit
Bit
Feb 29, 2008
PD3_5
PD3_7
PD3
PD3
PD3_4
X
X
X
0
0
1
1
PD3
X
X
X
0
0
1
1
Port P3_4/SDA/SCS
Port P3_5/SCL/SSCK
Port P3_7/SSO
Port P4_2/VREF
X
X
X
0
0
1
1
ADCON1
Clock Synchronous Serial I/O with Chip Select
SSCK output control
VCUT
Clock Synchronous Serial I/O with Chip Select
(Refer to Table 16.4 Association between
SSO output control
(Refer to Table 16.4 Association between
Communication Modes and I/O Pins.)
0
1
Communication Modes and I/O Pins.)
Page 66 of 485
CSS1
X
0
0
0
0
0
1
1
0
0
0
0
0
1
1
X
X
0
0
0
1
1
SSMR2
CSS0
Input port
Input port/VREF input
X
0
0
0
0
1
0
1
SSCK input control
SSO input control
IICSEL
PMR
0
0
0
0
1
0
0
X
X
X
X
0
0
0
0
1
0
0
1
0
0
ICCR1
ICE
IICSEL
X
X
X
X
0
0
1
PMR
SSMR2
SOOS
0
X
0
X
0
0
1
X
X
0
0
0
0
1
Input port
Output port
SCS input
SCS output
SDA input/output
ICCR1
ICE
Function
X
X
0
0
0
0
1
IICSEL
PMR
0
1
0
1
0
0
0
Input port
Output port
SSCK input
SSCK output
SCL input/output
(1)
(2)
(2)
Input port
Output port
SSO input
SSO output (CMOS output)
SSO output (N-channel open-drain
output)
(1)
7. Programmable I/O Ports
Function
(2)
(2)
(1)
Function
Function

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