R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 517

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
1.00
REVISION HISTORY
May 31, 2006
Date
362 to 375 17. Hardware LIN;
Page
287
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Figure 15.6 Registers U0C1 to U1C1, U1SR, and PMR;
16.2.1 Transfer Clock; “ φ ” → “f1” revised
16.2.5.2 Data Transmission;
16.2.6.2 Data Transmission;
Table 15.1 Clock Synchronous Serial I/O Mode Specifications revised
15.1 Clock Synchronous Serial I/O Mode;
15.2 Clock Asynchronous Serial I/O (UART) Mode;
Figure 15.11 Receive Timing Example in UART Mode;
Table 16.2 Clock Synchronous Serial I/O with Chip Select Specifications;
Figure 16.4 SSMR Register
Figure 16.7 SSMR2 Register revised
Figure 16.8 Registers SSTDR and SSRDR; SSTDR registers NOTE1 deleted
Figure 16.14 Sample Flowchart of Data Transmission (Clock
Synchronous Communication Mode) NOTE2 deleted
16.2.5.4 Data Transmission/Reception;
Figure 16.17 Sample Flowchart of Data Transmission/Reception (Clock
Synchronous Communication Mode) NOTE2 deleted
Figure 16.18 Initialization in 4-Wire Bus Communication Mode revised
Figure 16.47 Example of Register Setting in Master Receive Mode (I
bus Interface Mode) revised
Figure 17.1 Block Diagram of Hardware LIN revised
Figure 17.2 LINCR Register revised
Figure 17.3 LINST Register revised
Figure 17.4 Typical Operation when Sending a Header Field
Figure 17.5 Example of Header Field Transmission Flowchart (1) revised
Figure 17.6 Example of Header Field Transmission Flowchart (2) revised
17.4.2 Slave Mode (5) revised
Figure 17.7 Typical Operation when Receiving a Header Field revised
Figure 17.8 Example of Header Field Reception Flowchart (1) revised
Figure 17.9 Example of Header Field Reception Flowchart (2) revised
R8C/24 Group, R8C/25 Group Hardware Manual
U0C1 to U1C1 register NOTE2 added
“Table 15.3 ... The TXD0 pin ...” → “Table 15.3 ... The TXDi pin ...” revised
“Table 15.6 ... The TXD0 pin ...” → “Table 15.6 ... The TXDi pin ...” revised
“ φ ” → “f1” revised and NOTE2 deleted
“When setting the MCU is set as a slave device, ... enabled.” deleted
“When the MCU is set as the slave device, ... enabled.” deleted
“When the MCU is set as a slave device, ... enabled.” deleted
“Sync Break” → “Synch Break” and “Sync Field” → “Synch Field” revised
“RAIC” → “TRAIC” revised
“RI bit” → “IR bit” revised
C - 13
Description
Summary
2
C