R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 510

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
0.20
REVISION HISTORY
Jan 16, 2006
Date
387 to 389 18.4 A/D Conversion Cycles to 18.6 Inflow Current Bypass Circuit added
Page
249
251
252
253
255
256
259
260
264
275
281
285
286
287
295
300
358
377
378
390
391
392
393
395
398
Figure 14.102 Registers TRDOER1 to TRDOER2 in PWM3 Mode;
18.7 Notes on A/D Converter
19.2 Memory Map;
19.4.2.4 FMSTP Bit revised
Figure 14.104 TRDCR0 Register in PWM3 Mode NOTE1 deleted
Figure 14.105 TRDSR0 Register in PWM3 Mode revised
Figure 14.106 TRDIER0 Register in PWM3 Mode revised
Table 14.34 TRDGRji Register Functions in PWM3 Mode revised
Figure 14.109 Operating Example of PWM3 Mode revised
14.3.12.1 TRDSTR Register (i = 0 or 1) added
14.3.12.4 “Count Clock Source Switch” → “Count Source Switch”
revised
14.3.12.9 Count Source fOCO40M added
Table 14.39 Output Compare Mode Specifications revised
Figure 14.132 Setting Example in Real-Time Clock Mode revised
Figure 15.3 Registers U0TB to U1TB and U0RB to U1RB revised
Figure 15.4 Registers U0BRG to U1BRG and U0MR to U1MR; U0BRG
to U1BRG register revised
Figure 15.5 Registers U0C0 to U1C0 NOTE1 added
Table 15.5 Registers Used and Settings for UART Mode;
Table 16.1 Mode Selections revised
Figure 16.46 Example of Register Setting in Master Transmit Mode
(Clock Synchronous Serial Mode);
Table 18.1 Performance of A/D converter revised
Figure 18.1 Block Diagram of A/D Converter;
Table 19.1 Flash Memory Version Performance;
• Program and Erase Endurance:(Program area) → (Program ROM),
• NOTE3 added
Figure 19.1 Flash Memory Block Diagram for R8C/24 Group revised
Figure 19.2 Flash Memory Block Diagram for R8C/25 Group revised
Figure 19.4 OFS Register; NOTE1 revised and NOTE3 added
R8C/24 Group, R8C/25 Group Hardware Manual
TRDOER2 register: NOTE1 added
UiBRG: “ − ” → “0 to 7” revised
“ • Set the IICSEL bit in the PMR register to 1” added
“VSS” → “AVSS” and “Vref” → “Vcom” revised
“ • Connect 0.1 µ F capacitor ... VSS pin.” →
“ • Connect 0.1 µ F capacitor ... AVSS pin.” revised
“The user ROM ... area ... Block A and B.” →
“The user ROM ... area (program ROM) ... Block A and B (data flash).”
revised
C - 6
Description
Summary
(Data area) → (Data flash) revised