R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 195

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 14.27
14.3.1
Table 14.21
i = 0 or 1
NOTE:
f1, f2, f4, f8, f32
fOCO40M
External signal input
to TRDCLK pin
1. The count source fOCO40M can be used with VCC = 3.0 to 5.5 V.
Count Source
TRDCLK/
TRDIOA0
The count source selection method is the same in all modes. However, in PWM3 mode, the external clock
cannot be selected.
Set the pulse width of the external clock which inputs to the TRDCLK pin to 3 cycles or above of the operation
clock of timer RD (refer to Table 14.11 Timer RD Operation Clocks).
When selecting fOCO40M for the count source, set the FRA00 bit in the FRA0 register to 1 (high-speed on-
chip oscillator on) before setting bits TCK2 to TCK0 in the TRDCRi register (i = 0 or 1) to 110b (fOCO40M).
fOCO40M
Feb 29, 2008
Count Sources
(1)
f32
f1
f2
f4
f8
Count Source Selection
Block Diagram of Count Source
TCK2 to TCK0, CKEG1 to CKEG0: Bits in TRDCRi register
STCLK: Bit in TRDFCR register
STCLK = 1
STCLK = 0
The count source is selected by bits TCK2 to TCK0 in the TRDCRi register.
The FRA00 bit in the FRA0 register is set to 1 (high-speed on-chip oscillator
frequency).
Bits TCK2 to TCK0 in the TRDCRi register is set to 110b (fOCO40M).
The STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
Bits TCK2 to TCK0 in the TRDCRi register are set to 101b
(count source: external clock).
The valid edge is selected by bits CKEG1 to CKEG0 in the TRDCRi register.
The PD2_0 bit in the PD2 register is set to 0 (input mode).
Page 176 of 485
CKEG1 to CKEG0
Valid edge
selected
= 011b
= 010b
= 100b
= 110b
= 001b
TCK2 to TCK0
TRDIOA0 I/O or programmable I/O port
= 000b
= 101b
Selection
Count source
TRDi register
14. Timers