R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 147

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 13.2
Option Function Select Register
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
NOTES:
b7 b6 b5 b4
1.
2.
3. If the block including the OFS register is erased, FFh is set to the OFS register.
1
0 0
The OFS register is on the flash memory. Write to the OFS register w ith a program. After w riting is completed, do not
w rite additions to the OFS register.
To use the pow er-on reset, set the LVD0ON bit to 0 (voltage monitor 0 reset enabled after reset).
Feb 29, 2008
1
b3 b2 b1 b0
Registers OFS and WDC
1
Bit Symbol
Bit Symbol
CSPROINI
ROMCP1
LVD0ON
WDTON
ROMCR
(b4-b0)
Symbol
Symbol
WDC7
WDC
OFS
(b1)
(b4)
(b6)
(b5)
(b6)
Page 128 of 485
—
—
—
—
—
—
Watchdog timer start
select bit
Reserved bit
ROM code protect
disabled bit
ROM code protect bit
Reserved bit
Voltage detection 0
circuit start bit
Reserved bit
Count source protect
mode after reset select
bit
High-order bits of w atchdog timer
Reserved bit
Reserved bit
Prescaler select bit
(1)
Address
Bit Name
Address
Bit Name
0FFFFh
000Fh
(2)
0 : Starts w atchdog timer automatically after reset
1 : Watchdog timer is inactive after reset
Set to 1.
0 : ROM code protect disabled
1 : ROMCP1 enabled
1 : ROM code protect disabled
Set to 1.
0 : Voltage monitor 0 reset enabled after hardw are
1 : Voltage monitor 0 reset disabled after hardw are
Set to 1.
0 : Count source protect mode enabled after reset
1 : Count source protect mode disabled after reset
Set to 0. When read, the content is undefined.
Set to 0.
0 : Divide-by-16
1 : Divide-by-128
0 : ROM code protect enabled
reset
reset
When Shipping
After Reset
00X11111b
Function
Function
FFh
(3)
13. Watchdog Timer
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO