R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 315

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
Figure 15.7
• Example of transmit timing (when internal clock is selected)
• Example of receive timing (when external clock is selected)
The above applies under the following settings:
The following conditions are met when “H” is applied to the CLKi pin before receiving data:
fEXT: Frequency of external clock
i = 0 or 1
The above applies under the following settings:
TE bit in UiC1
register
TI bit in UiC1
register
CLKi
TXDi
TXEPT bit in
UiC0 register
IR bit in SiTIC
register
RE bit in UiC1
register
TE bit in UiC1
register
TI bit in UiC1
register
CLKi
RXDi
RI bit in UiC1
register
IR bit in SiRIC
register
• CKDIR bit in UiMR register = 1 (external clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• TE bit in UiC1 register = 1 (enables transmit)
• RE bit in UiC1 register = 1 (enables receive)
• Write dummy data to the UiTB register
• CKDIR bit in UiMR register = 0 (internal clock)
• CKPOL bit in UiC0 register = 0 (output transmit data at the falling edge and input receive data at the rising edge of the transfer clock)
• UiIRS bit in UiC1 register = 0 (an interrupt request is generated when the transmit buffer is empty)
Transfer clock
Feb 29, 2008
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Transmit and Receive Timing Example in Clock Synchronous Serial I/O Mode
Write dummy data to UiTB register
D0
D0
Transfer from UARTi receive register to
D1
D1
Set data in UiTB register
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D2
D2
TCLK
D3
D3
Transfer from UiTB register to UARTi transmit register
1/fEXT
D4
D4
UiRB register
TC
Receive data is taken in
D5
D5
D6
D6
Set to 0 when interrupt request is acknowledged, or set by a program
D7
D7
Transfer from UiTB register to UARTi transmit register
D0 D1
Set to 0 when interrupt request is acknowledged, or set by a program
D0 D1
D2
D3
D2
Read out from UiRB register
D3
D4
TC=TCLK=2(n+1)/fi
D5
D4
fi: Frequency of UiBRG count source (f1, f8, f32)
n: Setting value to UiBRG register
D6
D5
D7
Stop pulsing because the TE bit is set to 0
D0 D1
D2
D3
D4
15. Serial Interface
D5
D6
D7