R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 354

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
16.3
Table 16.5
NOTE:
Communication formats • I
I/O pins
Transfer clocks
Receive error detection • Overrun error detection (clock synchronous serial format)
Interrupt sources
Select functions
The I
Philips I
Table 16.5 lists the I
Figure 16.23 shows the External Circuit Connection Example of Pins SCL and SDA. Figures 16.24 to 16.31 show
the registers associated with the I
* I
1. All sources use one interrupt vector for I
2
C bus is a trademark of Koninklijke Philips Electronics N. V.
2
I
C bus interface is the circuit that performs serial communication based on the data transfer format of the
Feb 29, 2008
2
2
C bus Interface
C bus.
Item
I
2
C bus Interface Specifications
2
C bus Interface Specifications, Figure 16.22 shows a Block Diagram of I
Page 335 of 485
• Clock synchronous serial format
SCL (I/O): Serial clock I/O pin
SDA (I/O): Serial data I/O pin
• When the MST bit in the ICCR1 register is set to 0
• When the MST bit in the ICCR1 register is set to 1
• I
• Clock synchronous serial format ...... 4 sources
• I
• Clock synchronous serial format
2
- Selectable as master/slave device
- Continuous transmit/receive operation (because the shift register, transmit
- Start/stop conditions are automatically generated in master mode
- Automatic loading of acknowledge bit during transmission
- Bit synchronization/wait function (In master mode, the state of the SCL
- Support for direct drive of pins SCL and SDA (N-channel open drain output)
- Continuous transmit/receive operation (because the shift register, transmit
The external clock (input from the SCL pin)
The internal clock selected by bits CKS0 to CKS3 in the ICCR1 register
(output from the SCL pin)
Indicates an overrun error during reception. When the last bit of the next data
item is received while the RDRF bit in the ICSR register is set to 1 (data in the
ICDRR register), the AL bit is set to 1.
2
Transmit data empty (including when slave address matches), transmit ends,
receive data full (including when slave address matches), arbitration lost,
NACK detection, and stop condition detection.
Transmit data empty, transmit ends, receive data full and overrun error
2
- Selectable output level for acknowledge signal during reception
- MSB-first or LSB-first selectable as data transfer direction
C bus format
C bus format .................................. 6 sources
C bus format
data register, and receive data register are independent)
data register, and receive data register are independent)
signal is monitored per bit and the timing is synchronized automatically. If
the transfer is not possible yet, the SCL signal goes “L” and the interface
stands by.)
2
C bus interface.
2
C bus interface.
Specification
16. Clock Synchronous Serial Interface
(1)
(1)
2
C bus interface, and