R5F21257SNFP#U0 Renesas Electronics America, R5F21257SNFP#U0 Datasheet - Page 391

• Manufacturer Part Number: R5F21257SNFP#U0
• Description: IC R8C/25 MCU FLASH 52LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/25r

Specifications of R5F21257SNFP#U0

• Core Processor: R8C
• Core Size: 16/32-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SIO, SSU, UART/USART
• Peripherals: POR, Voltage Detect, WDT
• Number Of I /o: 41
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 2.5K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 52-LQFP
• For Use With: R0K521256S000BE - KIT EVAL STARTER FOR R8C/25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R8C/24 Group, R8C/25 Group
Rev.3.00
REJ09B0244-0300
17.4
Figure 17.4
17.4.1
IR bit in the TRAIC
SBDCT flag in the
Figure 17.4 shows typical operation of the hardware LIN when transmitting a header field in master mode.
Figures 17.5 and 17.6 show a flowchart of the procedure for transmitting a header field.
When transmitting a header field, the hardware LIN operates as described below.
LINST register
Functional Description
(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in software, the hardware
(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of
(3) The hardware LIN transmits 55h via UART0.
(4) The hardware LIN transmits an ID field via UART0 after it finishes sending 55h.
(5) The hardware LIN performs communication for a response field after it finishes sending the ID field.
Feb 29, 2008
TXD0 pin
Master Mode
LIN outputs “L” level from the TXD0 pin for the period that is set in registers TRAPRE and TRA for
timer RA.
the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the
LINCR register is set to 1, it generates a timer RA interrupt.
register
Typical Operation when Sending a Header Field
1
0
1
0
1
0
The above applies under the following conditions:
LINE = 1, MST = 1, SBIE = 1
Page 372 of 485
(1)
Synch Break
(2)
(3)
Set by writing 1 to the
B1CLR bit in the LINST
register
Cleared to 0 upon
acceptance of interrupt
request or by a program
Synch Field
(4)
IDENTIFIER
17. Hardware LIN
(5)