M38039FFHFP#U0 Renesas Electronics America, M38039FFHFP#U0 Datasheet - Page 110

• Manufacturer Part Number: M38039FFHFP#U0
• Description: IC 740 MCU FLASH 60K 64QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039FFHFP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H)
Rev.3.11
REJ03B0017-0311
Notes on Interrupts
1. Change of relevant register settings
When the setting of the following registers or bits is changed, the
interrupt request bit may be set to “1”. When not requiring the
interrupt occurrence synchronized with these setting, take the
following sequence.
• Interrupt edge selection register (address 003A
• Timer XY mode register (address 0023
• Timer Z mode register (address 002A
Set the above listed registers or bits as the following sequence.
Fig 88. Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit may be set
to “1”.
• When setting external interrupt active edge
• When switching interrupt sources of an interrupt vector
Concerned register: Interrupt edge selection register
address where two or more interrupt sources are allocated.
Concerned register: Interrupt source selection register
Set the corresponding interrupt enable bit to “0” (disabled).
Set the corresponding interrupt enable bit to “1” (enabled).
Set the interrupt edge select bit (active edge switch bit)
or the interrupt (source) select bit to “1”.
Set the corresponding interrupt request bit to “0”
Apr 5, 2006
NOP (one or more instructions)
(no interrupt request issued).
(address 003A
Timer XY mode register (address 0023
Timer Z mode register (address 002A
(address 0039
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16
16
)
)
16
16
)
)
16
)
16
16
)
)
2. Check of interrupt request bit
When executing the BBC or BBS instruction to an interrupt
request bit of an interrupt request register immediately after this
bit is set to “0”, execute one or more instructions before
executing the BBC or BBS instruction.
Fig 89. Sequence of check of interrupt request bit
<Reason>
If the BBC or BBS instruction is executed immediately after an
interrupt request bit of an interrupt request register is cleared to
“0”, the value of the interrupt request bit before being cleared to
“0” is read.
Clear the interrupt request bit to “0” (no interrupt issued)
Execute the BBC or BBS instruction
NOP (one or more instructions)