M38039FFHFP#U0 Renesas Electronics America, M38039FFHFP#U0 Datasheet - Page 19

• Manufacturer Part Number: M38039FFHFP#U0
• Description: IC 740 MCU FLASH 60K 64QFP
• Manufacturer: Renesas Electronics America
• Series: 740/38000r

Specifications of M38039FFHFP#U0

• Core Processor: 740
• Core Size: 8-Bit
• Speed: 16.8MHz
• Connectivity: SIO, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

3803 Group (Spec.H)
Rev.3.11
REJ03B0017-0311
I/O PORTS
The I/O ports have direction registers which determine the
input/output direction of each individual pin. Each bit in a
direction register corresponds to one pin, and each pin can be set
to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin
becomes an input pin. When “1” is written to that bit, that pin
becomes an output pin.
If data is read from a pin which is set to output, the value of the
port output latch is read, not the value of the pin itself. Pins set to
Table 9
NOTES:
P0
P1
P1
P1
P2
P3
P3
P3
P3
P3
P3
P3
P4
P4
P4
P4
P4
P4
P4
P4
P5
P5
P5
P5
P5
P5
P5
P5
P6
1. Refer to the applicable sections how to use double-function ports as function I/O ports.
2. Make sure that the input level at each pin is either 0 V or V
1
0
0
2
0
0
1
2
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
/INT
/INT
/AN
−P1
/LED
/DA
/DA
, P3
/R
/T
/S
/S
/INT
/INT
/INT
/INT
/R
/T
/S
/S
/S
/S
/S
/S
/CNTR
/CNTR
/PWM
/INT
/AN
When an input level is at an intermediate potential, a current will flow from V
X
X
CLK3
RDY3
CLK1
RDY1
IN2
OUT2
CLK2
RDY2
X
X
D
D
D
D
8
1
2
0
01
7
3
41
40
00
1
2
3
−P0
3
1
−P6
Pin
0
3
1
−P2
/X
/X
/CNTR
0
1
I/O port function
COUT
CIN
7
7
/AN
/AN
Apr 5, 2006
7
/LED
15
7
2
7
Port P0 Input/output,
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Name
individual
bits
Page 17 of 113
Output
Input/
CMOS compatible
input level
CMOS 3-state
output
CMOS compatible
input level
N-channel
open-drain output
CMOS compatible
input level
CMOS 3-state
output
I/O Structure
CC
during execution of the STP instruction.
A/D converter input
External interrupt input
D/A converter output
Serial I/O3 function I/O
External interrupt input
Sub-clock generating circuit
External interrupt input
Serial I/O1 function I/O
Serial I/O1 function I/O
Timer Z function I/O
Serial I/O2 function I/O
Timer X, Y function I/O
PWM output
External interrupt input
A/D converter input
input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
By setting the port P0 pull-up control register (address 0FF0
to the port P6 pull-up control register (address 0FF6
control pull-up with a program. However, the contents of these
registers do not affect ports programmed as the output ports.
Non-Port Function
CC
to V
SS
through the input-stage gate.
AD/DA control register
Interrupt edge selection register
AD/DA control register
Serial I/O3 control register
UART3 control register
Interrupt edge selection register
CPU mode register
Interrupt edge selection register
Serial I/O1 control register
UART1 control register
Serial I/O1 control register
Timer Z mode register
Serial I/O2 control register
Timer XY mode register
PWM control register
Interrupt edge selection register
AD/DA control register
Related SFRs
16
) ports can
Ref.
(10)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(11)
No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(2)
(6)
(7)
(8)
(2)
(1)
16
)